| Name / Title | Added | Expires | Hits | Comments | Syntax | |
|---|---|---|---|---|---|---|
| Synchronized S-DES Design | Jan 19th, 2017 | Never | 159 | 0 | VeriLog | - |
| Asynchronized S-DES Design | Jan 19th, 2017 | Never | 148 | 0 | VeriLog | - |
| Synchronized S-DES Design | Jan 19th, 2017 | Never | 134 | 0 | VeriLog | - |
| uprocessorProject | Dec 19th, 2016 | Never | 131 | 0 | ASM (NASM) | - |
| Digital Logic II Final Project | Dec 25th, 2013 | Never | 165 | 0 | VHDL | - |