ya3ny maslan law fih AND gate ,hate3melo kda :
entity AND_GATE is
port (A,B : in std_vector(4 downto 0 );
Z: out std_vector(4 downto 0););
end AND_GATE ;

architecture behavior of AND_GATE is

BEGIN
Z(0) <= A(0) AND B(0);
Z(1) <= A(1) AND B(1);
Z(2) <= A(2) AND B(2);
Z(3) <= A(3) AND B(3);
end behavior;