View difference between Paste ID: c2chTc5f and EaGRFZpU

-library ieee;
+ya3ny maslan law fih AND gate ,hate3melo kda :
-use ieee.std_logic_1164.all;
+entity AND_GATE is
 port (A,B : in std_vector(4 downto 0 );
-entity Carry_Look_Ahead_adder is
+Z: out std_vector(4 downto 0););
-     port (A0,A1,A2,A3,B0,B1,B2,B3,SEL : in std_logic;
+end AND_GATE ;
-           ZO,Z1,Z2,Z3: out std_logic);
+
-     end Carry_Look_Ahead_adder;
+architecture behavior of AND_GATE is
-
+
-architecture behavior of Carry_Look_Ahead_adder is
+BEGIN
-begin
+Z(0) <= A(0) AND B(0);
-if (SEL = '1') then
+Z(1) <= A(1) AND B(1);
-Z0 <= A0 and B0;
+Z(2) <= A(2) AND B(2);
-Z1 <= A1 and B1;
+Z(3) <= A(3) AND B(3);
-Z2 <= A2 and B2;
+end behavior;