library ieee;
use ieee.std_logic_1164.all;

entity Carry_Look_Ahead_adder is
     port (A0,A1,A2,A3,B0,B1,B2,B3,SEL : in std_logic;
           ZO,Z1,Z2,Z3: out std_logic);
     end Carry_Look_Ahead_adder;

architecture behavior of Carry_Look_Ahead_adder is
begin
if (SEL = '1') then
Z0 <= A0 and B0;
Z1 <= A1 and B1;
Z2 <= A2 and B2;
Z3 <= A3 and B3;
end if ;
if (SEL = '0') then
Z0 <= A0 or B0;
Z1 <= A1 or B1;
Z2 <= A2 or B2;
Z3 <= A3 or B3;
end if ;
     end behavior;