Synchronized S-DES Design

/*
    Simplified Data Encryption Standard (S-DES)
    8-bit 2-round block cipher symmetric-key algorithm using 10-bit key.
    Encryption/Decryption routine takes total of 7 clock cycles
*/


module SDES(    en,             // Enable Bit
                CLK,            // Clock signal
                Key,            // 10-bit Key
                plaintext,      // 8-bit data block
                encrypt,        // Encryption flag, 1 for encryption, 0 for decryption
                ciphertext      // 8-bit data block
                );

    input           en;
    input           encrypt;
    input           CLK;
    input   [0:7]   plaintext;
    input   [0:9]   Key;
    output  [0:7]   ciphertext;

    // Internal signals
    reg     [0:7]   sw_out, iip_out, xor_f1, xor_f2, p4_in, s0_out, s1_out;
    reg     [0:2]   cnt = 3'b000;
    reg     [0:7]   Key1, Key2;

    assign ciphertext = (en)?(iip_out):(8'b0);

    always@(cnt)
    begin
        if(cnt == 3'b110)
            cnt = 3'b000;
    end

    always@(posedge CLK)
    begin
        Key1 = {Key[0], Key[6], Key[8], Key[3], Key[7], Key[2], Key[9], Key[5]};
        Key2 = {Key[7], Key[2], Key[5], Key[4], Key[9], Key[1], Key[8], Key[0]};
    end

    // Feistel Function Round One
    always@(posedge CLK)
    begin

        if(cnt < 3'b011)
        begin

            if(encrypt)
            begin
                xor_f1  <= { plaintext[6] ^ Key1[0], plaintext[3] ^ Key1[1], plaintext[7] ^ Key1[2], plaintext[4] ^ Key1[3] };
                xor_f2  <= { plaintext[7] ^ Key1[4], plaintext[4] ^ Key1[5], plaintext[6] ^ Key1[6], plaintext[3] ^ Key1[7] };
            end
            else
            begin
                xor_f1  <= { plaintext[6] ^ Key2[0], plaintext[3] ^ Key2[1], plaintext[7] ^ Key2[2], plaintext[4] ^ Key2[3] };
                xor_f2  <= { plaintext[7] ^ Key2[4], plaintext[4] ^ Key2[5], plaintext[6] ^ Key2[6], plaintext[3] ^ Key2[7] };
            end

            p4_in  <= {s0_out, s1_out};

            cnt <= cnt + 1'b1;

        end
    end

    // Feistel Function Round Two
    always@(posedge CLK)
    begin

        if(cnt == 3'b011)
        begin

            if(encrypt)
            begin
                xor_f1 <= { p4_in[0] ^ plaintext[0] ^ Key2[0], p4_in[1] ^ plaintext[1] ^ Key2[1], p4_in[3] ^ plaintext[5] ^ Key2[2], p4_in[2] ^ plaintext[2] ^ Key2[3] };
                xor_f2 <= { p4_in[3] ^ plaintext[5] ^ Key2[4], p4_in[2] ^ plaintext[2] ^ Key2[5], p4_in[0] ^ plaintext[0] ^ Key2[6], p4_in[1] ^ plaintext[1] ^ Key2[7] };
            end
            else
            begin
                xor_f1 <= { p4_in[0] ^ plaintext[0] ^ Key1[0], p4_in[1] ^ plaintext[1] ^ Key1[1], p4_in[3] ^ plaintext[5] ^ Key1[2], p4_in[2] ^ plaintext[2] ^ Key1[3] };
                xor_f2 <= { p4_in[3] ^ plaintext[5] ^ Key1[4], p4_in[2] ^ plaintext[2] ^ Key1[5], p4_in[0] ^ plaintext[0] ^ Key1[6], p4_in[1] ^ plaintext[1] ^ Key1[7] };
            end

            p4_in <= {s0_out, s1_out};

            iip_out <= {    p4_in[0] ^ plaintext[6],
                            p4_in[1] ^ plaintext[3],
                            p4_in[2] ^ plaintext[4],
                            p4_in[1] ^ plaintext[1],
                            p4_in[2] ^ plaintext[2],
                            p4_in[3] ^ plaintext[7],
                            p4_in[0] ^ plaintext[0],
                            p4_in[3] ^ plaintext[5] };

            cnt <= cnt + 1'b1;
        end
    end

    // S0 Box
    always@(xor_f1)
    begin
        case(xor_f1)
            4'b0000: s0_out = 2'b01;
            4'b0001: s0_out = 2'b11;
            4'b0010: s0_out = 2'b00;
            4'b0011: s0_out = 2'b10;
            4'b0100: s0_out = 2'b11;
            4'b0101: s0_out = 2'b01;
            4'b0110: s0_out = 2'b10;
            4'b0111: s0_out = 2'b00;
            4'b1000: s0_out = 2'b00;
            4'b1001: s0_out = 2'b11;
            4'b1010: s0_out = 2'b10;
            4'b1011: s0_out = 2'b01;
            4'b1100: s0_out = 2'b01;
            4'b1101: s0_out = 2'b11;
            4'b1110: s0_out = 2'b11;
            4'b1111: s0_out = 2'b10;
        endcase
    end

    // S1 Box
    always@(xor_f2)
    begin
        case(xor_f2)
            4'b0000: s1_out = 2'b00;
            4'b0001: s1_out = 2'b10;
            4'b0010: s1_out = 2'b01;
            4'b0011: s1_out = 2'b00;
            4'b0100: s1_out = 2'b10;
            4'b0101: s1_out = 2'b01;
            4'b0110: s1_out = 2'b11;
            4'b0111: s1_out = 2'b11;
            4'b1000: s1_out = 2'b11;
            4'b1001: s1_out = 2'b10;
            4'b1010: s1_out = 2'b00;
            4'b1011: s1_out = 2'b01;
            4'b1100: s1_out = 2'b01;
            4'b1101: s1_out = 2'b00;
            4'b1110: s1_out = 2'b00;
            4'b1111: s1_out = 2'b11;
        endcase
    end

endmodule