library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
-- add the off directive right after the ieee libraries and before the Xilinx CoreLib
-- synopsys translate_off

Library XilinxCoreLib;

-- add the on directive right before the entity declaration
-- synopsys translate_on

entity MUX_2_1 is
Port (
a,b,S : in std_logic;
O : out std_logic;
);
end MUX_2_1;

architecture Behavioral of MUX_2_1 is
begin
if S = '0' then
          O <= a;
else
    O <= b;
end if;
end Behavioral;