`timescale 1ns / 1ps
module clkdiv_tb;
reg clk,rst;
reg[1:0] sw;
wire out;

clkdiv clkdiv_inst(.clk(clk),.rst(rst),.sw(sw),.out(out));

always
    #5 clk =  ~clk;

initial
begin
    sw = 2'b00;
    clk =0;
    rst =1;
    #10 rst=0;
    #10
    sw = 2'b00;
    #100
    sw = 2'b01;
    #100
    sw = 2'b10;
    #100
    sw = 2'b11;
    #100;
    $finish;
end

endmodule