Digital Logic II Final Project

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity control is
   Port (
        clk_in  : in   STD_LOGIC;
        reset   : in   STD_LOGIC;
        ot      : inout  STD_LOGIC_VECTOR (3 downto 0);
        pb      : in   STD_LOGIC_VECTOR (3 downto 0);
        ss0     : in   STD_LOGIC;
        ss1     : in   STD_LOGIC;
        leds    : inout  STD_LOGIC_VECTOR (3 downto 0);
        seg     : out STD_LOGIC_VECTOR (6 downto 0)
        );
end control;

architecture Behavioral of control is
    signal clk_out,temporal: STD_LOGIC;
    signal counter : integer := 0;
    type state_type is (s0,s1,s2,s3);
    signal current_s,next_s: state_type;
    signal lol : std_logic_vector(3 downto 0);
--   signal S_led : STD_LOGIC_VECTOR (3 downto 0) := "0000";
begin
    frequency_divider: process (reset, clk_in) begin
        if (reset = '1') then
            temporal <= '0';
            counter <= 0;
        elsif rising_edge(clk_in) then
            if (counter = 16666666) then
                temporal <= NOT(temporal);
                counter <= 0;
            else
                counter <= counter + 1;
            end if;
        end if;
    end process;

    clk_out <= temporal;

    process (clk_out,reset)
     begin

        if (reset = '0') then
            current_s <= next_s;
        else
            current_s <= s0;
        end if;
     end process;

    process (ss0,ss1,current_s) begin
            case current_s is
            when s0 =>
                if (ss1 = '0' and ss0 = '0' ) then
                    ot <= "0001";
                elsif (ss1 = '0' and ss0 = '1' ) then
                    ot <= "1000";
                elsif (ss1 = '1' and ss0 = '0' ) then
                    ot <= "0001";
                elsif (ss1 = '1' and ss0 = '1' ) then
                    ot <= "0001";
                end if;
                next_s <= s1;
            when s1 =>
                if (ss1 = '0' and ss0 = '0' ) then
                    ot <= "0010";
                elsif (ss1 = '0' and ss0 = '1' ) then
                    ot <= "0100";
                elsif (ss1 = '1' and ss0 = '0' ) then
                    ot <= "0100";
                elsif (ss1 = '1' and ss0 = '1' ) then
                    ot <= "1000";
                end if;
                next_s <= s2;
            when s2 =>
                if (ss1 = '0' and ss0 = '0' ) then
                    ot <= "0100";
                elsif (ss1 = '0' and ss0 = '1' ) then
                    ot <= "0010";
                elsif (ss1 = '1' and ss0 = '0' ) then
                    ot <= "0010";
                elsif (ss1 = '1' and ss0 = '1' ) then
                    ot <= "0010";
                end if;
                next_s <= s3;
            when s3 =>
                if (ss1 = '0' and ss0 = '0' ) then
                    ot <= "1000";
                elsif (ss1 = '0' and ss0 = '1' ) then
                    ot <= "0001";
                elsif (ss1 = '1' and ss0 = '0' ) then
                    ot <= "1000";
                elsif (ss1 = '1' and ss0 = '1' ) then
                    ot <= "0100";
                end if;
                next_s <= s0;
            end case;
    end process;
    process (pb,ot,leds)
    begin
        while (pb = "0000") loop
        end loop;
        lol <= pb AND ot;
        if ( (lol = "1000") or (lol = "0100") or (lol = "0010") or (lol = "0001")) then
            leds <= leds + "1";
        end if;
    end process;
    process (leds)
    begin
        case leds is
             when "0000"=>seg<="0000001"; -- '0'
             when "0001"=>seg<="1111001"; -- '1'
             when "0010"=>seg<="0100100"; -- '2'
             when "0011"=>seg<="0110000"; -- '3'
             when "0100"=>seg<="0011001"; -- '4'
             when "0101"=>seg<="0010010"; -- '5'
             when "0110"=>seg<="0000010"; -- '6'
             when "0111"=>seg<="1111000"; -- '7'
             when "1000"=>seg<="0000000"; -- '8'
             when "1001"=>seg<="0010000"; -- '9'
             when "1010"=>seg<="0100000"; -- 'A'
             when "1011"=>seg<="0000011"; -- 'B'
             when "1100"=>seg<="1000110"; -- 'C'
             when "1101"=>seg<="0100001"; -- 'D'
             when "1110"=>seg<="0000100"; -- 'E'
             when "1111"=>seg<="0001110"; -- 'F'
             when others=>seg<="1111111"; -- 'NULL'
        end case;
    end process;
end Behavioral;