`timescale 1ns/1ps
module tb;
reg[3:0] A,B;
reg Ci;
wire[7:0] S;

mymult myinst(.A(A),.B(B),.out(S));

initial
begin
    A = 4'b0000;
    B = 4'b0000;
    Ci = 1'b0;
    $monitor("A: %d  B: %d  ==> Out: %d\n",A,B,S);
end

initial
begin
    #20
    A = 2;
    B = 3;
    #5
    A = 1;
    B = 5;
    #5
    A = 0;
    B = 6;
    #5
    A = 10;
    B = 1;
    #5
    A = 10;
    B = 10;
    #5
    A = 4;
    B = 3;
    #5
    A = 15;
    B = 15;
    $finish;
end

endmodule