// D-Flip Flop implementation

module dff(input clk,rst,d, output reg q);
always@(posedge clk or posedge rst)
begin
    if (rst)
        q = 1'b0;
    else
        q = d;
end
endmodule

// 4x1 Multiplexer

module mux4x1(input wire[3:0] x, input wire[1:0] cnt, output out);

assign out = (cnt == 2'b00)?(x[0]):((cnt == 2'b01)?(x[1]):((cnt == 2'b10)?(x[2]):(x[3]))) ;

endmodule

// Clock Divider Circuit with controlling switch

module clkdiv(input clk,rst, input wire[1:0] sw, output out);

wire[26:0] clkdiv;
wire[26:0] din;


dff dff_int0(.clk(clk),.rst(rst),.d(din[0]),.q(clkdiv[0]));

genvar i;
generate
    for(i=1;i<26;i=i+1)
        dff dff_inst(.clk(clkdiv[i-1]),.rst(rst),.d(din[i]),.q(clkdiv[i]));
endgenerate

mux4x1 mux_inst(.x({clkdiv[23],clkdiv[24],clkdiv[25],clkdiv[26]}),.cnt(sw),.out(out));

assign din = ~clkdiv;

endmodule