library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY MUX_2_1 IS
PORT
(
a,b,S : IN std_logic;
O : OUT std_logic;
);
END MUX_2_1;

ARCHITECTURE Behavioral OF MUX_2_1 IS
begin
if S = '0' then
          O <= a;
else
    O <= b;
end if;
end Behavioral;