***Single Bit***

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ADDONE is
Port ( a : in std_logic;
b : in std_logic;
cin : in std_logic;
s : out std_logic;
end ADDONE;

architecture Behavioral of ADDONE is

begin
s<=(a xor (b xor cin));

end Behavioral;

***Mux 2 to 1***

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MUX_2_1 is
Port ( a,b,S : in std_logic;
O : out std_logic;
end MUX_2_1;

architecture Behavioral of MUX_2_1 is

begin
if (S='0') then
    O <= a;
else
    O <= b;
end if;

end Behavioral;

***OverAll Process***

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL


entity all_me is
Port ( a,b: in std_logic_vector(3 downto 0);
Cin : in std_logic;
Sel:in std_logic;
O : out std_logic_vector(3 downto 0);
Cout: out std_logic;
end all_me;

architecture Behavioral of all_me is
signal s0,g,p,c : std_logic_vector(3 downto 0);

begin
g(0) <= a(0) and b(0);
g(1) <= a(1) and b(1);
g(2) <= a(2) and b(2);
g(3) <= a(3) and b(3);
p(0) <= a(0) or b(0);
p(1) <= a(1) or b(1);
p(2) <= a(2) or b(2);
p(3) <= a(3) or b(3);
c(1) <= g(0) or (p(0) and Cin);
c(2) <= g(1) or (p(1) and c(1));
c(3) <= g(2) or (p(2) and c(2));
Cout <= g(3) or (p(3) and c(3));
bit1: ADDONE port map (a=>a(0), b=>b(0), s=>s0(0), cin=>Cin);
bit2: ADDONE port map (a=>a(1), b=>b(1), s=>s0(1), cin=>c(1));
bit3: ADDONE port map (a=>a(2), b=>b(2), s=>s0(2), cin=>c(2));
bit4: ADDONE port map (a=>a(3), b=>b(3), s=>s0(3), cin=>c(3));
E <= a(0) xor b(0);
F <= a(1) xor b(1);
G <= a(2) xor b(2);
H <= a(3) xor b(3);
bit5: MUX_2_1 port map (a=>E,b=>s0(0),S=>Sel,O=>O(0));
bit6: MUX_2_1 port map (a=>F,b=>s0(1),S=>Sel,O=>O(1));
bit7: MUX_2_1 port map (a=>G,b=>s0(2),S=>Sel,O=>O(2));
bit8: MUX_2_1 port map (a=>H,b=>s0(3),S=>Sel,O=>O(3));

end Behavioral;