Sidsh's Pastebin

1,189 42,096 0 3 years ago

Name / Title	Added	Expires	Hits	Syntax
Untitled	Dec 4th, 2024	Never	6,836	SystemVerilog	-
Untitled	Dec 1st, 2024	Never	133	None	-
function cache rajni	Dec 1st, 2024	Never	1,039	SystemVerilog	-
Untitled	Nov 8th, 2024	Never	153	None	-
Untitled	Nov 2nd, 2022	Never	499	None	-
Reporting system	Oct 29th, 2022	Never	1,478	SystemVerilog	-
sequencer.sv	Oct 29th, 2022	Never	1,496	SystemVerilog	-
monitor.sv	Oct 29th, 2022	Never	1,589	SystemVerilog	-
driver.sv	Oct 29th, 2022	Never	1,548	SystemVerilog	-
interface.sv	Oct 29th, 2022	Never	1,437	SystemVerilog	-
sequence.sv	Oct 29th, 2022	Never	1,660	SystemVerilog	-
sequence_item.sv	Oct 29th, 2022	Never	1,604	SystemVerilog	-
agent.sv	Oct 29th, 2022	Never	1,476	SystemVerilog	-
env.sv	Oct 29th, 2022	Never	1,509	SystemVerilog	-
test.sv	Oct 29th, 2022	Never	1,422	SystemVerilog	-
top.sv	Oct 29th, 2022	Never	1,375	SystemVerilog	-
Haskell blinker.	Jun 26th, 2022	Never	555	Haskell	-
Haskell Blinker	Jun 26th, 2022	Never	288	None	-
Haskell Blinker	Jun 26th, 2022	Never	516	Haskell	-
Blinker Haskell;	Jun 26th, 2022	Never	452	Haskell	-
WB_pwmaudiocontroller	Apr 10th, 2022	Never	981	SystemVerilog	-
Counter	Mar 25th, 2022	Never	288	None	-
LSA Documented 2.0	Mar 3rd, 2022	Never	459	VeriLog	-
LED Documented (sec*) 2.0	Mar 3rd, 2022	Never	278	None	-
ADC Documented 2.0	Mar 3rd, 2022	Never	467	VeriLog	-
LSA Documented 1.1	Mar 3rd, 2022	Never	467	VeriLog	-
LED Documented (sec*)	Mar 3rd, 2022	Never	466	VeriLog	-
ADC Documented	Mar 3rd, 2022	Never	330	VeriLog	-
UART messages added to Pick and Place+e	Mar 3rd, 2022	Never	314	VeriLog	-
Untitled	Mar 3rd, 2022	Never	318	VeriLog	-
Electromagnet enabled LSA	Mar 1st, 2022	Never	368	VeriLog	-
SM Path+Dep 1.2	Mar 1st, 2022	Never	316	VeriLog	-
Path Traversal+Deposition SM	Feb 28th, 2022	Never	315	VeriLog	-
SM Path Traversal 1.1	Feb 28th, 2022	Never	334	VeriLog	-
Path Traversal SM	Feb 27th, 2022	Never	344	VeriLog	-
Dijkstra Sep	Feb 11th, 2022	Never	374	VeriLog	-
Dijkstra_only	Feb 11th, 2022	Never	293	VeriLog	-
LSA Backup	Feb 10th, 2022	Never	310	None	-
LSA Hardcoded	Feb 10th, 2022	Never	329	VeriLog	-
LSA Hardcoded TB	Feb 10th, 2022	Never	314	VeriLog	-
Hardcoded LSA	Feb 10th, 2022	Never	342	VeriLog	-
Untitled	Feb 9th, 2022	Never	313	VeriLog	-
Untitled	Feb 9th, 2022	Never	305	VeriLog	-
LSA+Dijkstra 2.0	Feb 9th, 2022	Never	325	VeriLog	-
Dijkstra+LSA	Feb 8th, 2022	Never	311	VeriLog	-
Dijkstra Reference	Feb 7th, 2022	Never	322	VeriLog	-
Dijkstra tb	Feb 6th, 2022	Never	311	VeriLog	-
Dijkstra	Feb 6th, 2022	Never	291	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	285	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	277	VeriLog	-
Untitled	Feb 5th, 2022	Never	298	VeriLog	-
Dijkstra rough	Feb 4th, 2022	Never	293	VeriLog	-
Untitled	Feb 4th, 2022	Never	272	VeriLog	-
Untitled	Feb 4th, 2022	Never	293	C++	-
Untitled	Feb 4th, 2022	Never	277	VeriLog	-
LED	Feb 1st, 2022	Never	287	VeriLog	-
LED	Feb 1st, 2022	Never	281	VeriLog	-
LED	Feb 1st, 2022	Never	259	None	-
LED_tb	Feb 1st, 2022	Never	273	VeriLog	-
Untitled	Jan 31st, 2022	Never	309	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	314	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	266	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	308	VeriLog	-
Untitled	Jan 31st, 2022	Never	251	None	-
Documented LSA	Jan 31st, 2022	Never	305	VeriLog	-