Sidsh's Pastebin

1,363 47,044 0 4 years ago

Name / Title	Added	Expires	Hits	Syntax
Untitled	Dec 4th, 2024	Never	6,979	SystemVerilog	-
Untitled	Dec 1st, 2024	Never	199	None	-
function cache rajni	Dec 1st, 2024	Never	1,129	SystemVerilog	-
Untitled	Nov 8th, 2024	Never	230	None	-
Untitled	Nov 2nd, 2022	Never	554	None	-
Reporting system	Oct 29th, 2022	Never	1,555	SystemVerilog	-
sequencer.sv	Oct 29th, 2022	Never	1,567	SystemVerilog	-
monitor.sv	Oct 29th, 2022	Never	1,662	SystemVerilog	-
driver.sv	Oct 29th, 2022	Never	1,614	SystemVerilog	-
interface.sv	Oct 29th, 2022	Never	1,516	SystemVerilog	-
sequence.sv	Oct 29th, 2022	Never	1,740	SystemVerilog	-
sequence_item.sv	Oct 29th, 2022	Never	1,696	SystemVerilog	-
agent.sv	Oct 29th, 2022	Never	1,570	SystemVerilog	-
env.sv	Oct 29th, 2022	Never	1,579	SystemVerilog	-
test.sv	Oct 29th, 2022	Never	1,498	SystemVerilog	-
top.sv	Oct 29th, 2022	Never	1,444	SystemVerilog	-
Haskell blinker.	Jun 26th, 2022	Never	633	Haskell	-
Haskell Blinker	Jun 26th, 2022	Never	363	None	-
Haskell Blinker	Jun 26th, 2022	Never	596	Haskell	-
Blinker Haskell;	Jun 26th, 2022	Never	547	Haskell	-
WB_pwmaudiocontroller	Apr 10th, 2022	Never	1,064	SystemVerilog	-
Counter	Mar 25th, 2022	Never	364	None	-
LSA Documented 2.0	Mar 3rd, 2022	Never	532	VeriLog	-
LED Documented (sec*) 2.0	Mar 3rd, 2022	Never	354	None	-
ADC Documented 2.0	Mar 3rd, 2022	Never	515	VeriLog	-
LSA Documented 1.1	Mar 3rd, 2022	Never	549	VeriLog	-
LED Documented (sec*)	Mar 3rd, 2022	Never	559	VeriLog	-
ADC Documented	Mar 3rd, 2022	Never	420	VeriLog	-
UART messages added to Pick and Place+e	Mar 3rd, 2022	Never	368	VeriLog	-
Untitled	Mar 3rd, 2022	Never	401	VeriLog	-
Electromagnet enabled LSA	Mar 1st, 2022	Never	450	VeriLog	-
SM Path+Dep 1.2	Mar 1st, 2022	Never	401	VeriLog	-
Path Traversal+Deposition SM	Feb 28th, 2022	Never	376	VeriLog	-
SM Path Traversal 1.1	Feb 28th, 2022	Never	408	VeriLog	-
Path Traversal SM	Feb 27th, 2022	Never	422	VeriLog	-
Dijkstra Sep	Feb 11th, 2022	Never	439	VeriLog	-
Dijkstra_only	Feb 11th, 2022	Never	367	VeriLog	-
LSA Backup	Feb 10th, 2022	Never	371	None	-
LSA Hardcoded	Feb 10th, 2022	Never	413	VeriLog	-
LSA Hardcoded TB	Feb 10th, 2022	Never	402	VeriLog	-
Hardcoded LSA	Feb 10th, 2022	Never	428	VeriLog	-
Untitled	Feb 9th, 2022	Never	390	VeriLog	-
Untitled	Feb 9th, 2022	Never	371	VeriLog	-
LSA+Dijkstra 2.0	Feb 9th, 2022	Never	406	VeriLog	-
Dijkstra+LSA	Feb 8th, 2022	Never	387	VeriLog	-
Dijkstra Reference	Feb 7th, 2022	Never	381	VeriLog	-
Dijkstra tb	Feb 6th, 2022	Never	390	VeriLog	-
Dijkstra	Feb 6th, 2022	Never	360	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	371	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	329	VeriLog	-
Untitled	Feb 5th, 2022	Never	377	VeriLog	-
Dijkstra rough	Feb 4th, 2022	Never	357	VeriLog	-
Untitled	Feb 4th, 2022	Never	351	VeriLog	-
Untitled	Feb 4th, 2022	Never	365	C++	-
Untitled	Feb 4th, 2022	Never	366	VeriLog	-
LED	Feb 1st, 2022	Never	362	VeriLog	-
LED	Feb 1st, 2022	Never	343	VeriLog	-
LED	Feb 1st, 2022	Never	338	None	-
LED_tb	Feb 1st, 2022	Never	341	VeriLog	-
Untitled	Jan 31st, 2022	Never	376	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	379	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	338	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	397	VeriLog	-
Untitled	Jan 31st, 2022	Never	323	None	-
Documented LSA	Jan 31st, 2022	Never	376	VeriLog	-