Sidsh's Pastebin

720 20,565 0 2 years ago

Name / Title	Added	Expires	Hits	Syntax
Untitled	Nov 2nd, 2022	Never	301	None	-
Reporting system	Oct 29th, 2022	Never	1,053	SystemVerilog	-
sequencer.sv	Oct 29th, 2022	Never	1,017	SystemVerilog	-
monitor.sv	Oct 29th, 2022	Never	1,027	SystemVerilog	-
driver.sv	Oct 29th, 2022	Never	1,041	SystemVerilog	-
interface.sv	Oct 29th, 2022	Never	1,015	SystemVerilog	-
sequence.sv	Oct 29th, 2022	Never	1,073	SystemVerilog	-
sequence_item.sv	Oct 29th, 2022	Never	1,069	SystemVerilog	-
agent.sv	Oct 29th, 2022	Never	1,046	SystemVerilog	-
env.sv	Oct 29th, 2022	Never	1,047	SystemVerilog	-
test.sv	Oct 29th, 2022	Never	1,043	SystemVerilog	-
top.sv	Oct 29th, 2022	Never	1,063	SystemVerilog	-
Haskell blinker.	Jun 26th, 2022	Never	387	Haskell	-
Haskell Blinker	Jun 26th, 2022	Never	145	None	-
Haskell Blinker	Jun 26th, 2022	Never	353	Haskell	-
Blinker Haskell;	Jun 26th, 2022	Never	244	Haskell	-
WB_pwmaudiocontroller	Apr 10th, 2022	Never	709	SystemVerilog	-
Counter	Mar 25th, 2022	Never	130	None	-
LSA Documented 2.0	Mar 3rd, 2022	Never	292	VeriLog	-
LED Documented (sec*) 2.0	Mar 3rd, 2022	Never	122	None	-
ADC Documented 2.0	Mar 3rd, 2022	Never	293	VeriLog	-
LSA Documented 1.1	Mar 3rd, 2022	Never	298	VeriLog	-
LED Documented (sec*)	Mar 3rd, 2022	Never	278	VeriLog	-
ADC Documented	Mar 3rd, 2022	Never	161	VeriLog	-
UART messages added to Pick and Place+e	Mar 3rd, 2022	Never	145	VeriLog	-
Untitled	Mar 3rd, 2022	Never	135	VeriLog	-
Electromagnet enabled LSA	Mar 1st, 2022	Never	182	VeriLog	-
SM Path+Dep 1.2	Mar 1st, 2022	Never	158	VeriLog	-
Path Traversal+Deposition SM	Feb 28th, 2022	Never	167	VeriLog	-
SM Path Traversal 1.1	Feb 28th, 2022	Never	150	VeriLog	-
Path Traversal SM	Feb 27th, 2022	Never	148	VeriLog	-
Dijkstra Sep	Feb 11th, 2022	Never	200	VeriLog	-
Dijkstra_only	Feb 11th, 2022	Never	140	VeriLog	-
LSA Backup	Feb 10th, 2022	Never	147	None	-
LSA Hardcoded	Feb 10th, 2022	Never	153	VeriLog	-
LSA Hardcoded TB	Feb 10th, 2022	Never	155	VeriLog	-
Hardcoded LSA	Feb 10th, 2022	Never	153	VeriLog	-
Untitled	Feb 9th, 2022	Never	142	VeriLog	-
Untitled	Feb 9th, 2022	Never	140	VeriLog	-
LSA+Dijkstra 2.0	Feb 9th, 2022	Never	143	VeriLog	-
Dijkstra+LSA	Feb 8th, 2022	Never	142	VeriLog	-
Dijkstra Reference	Feb 7th, 2022	Never	149	VeriLog	-
Dijkstra tb	Feb 6th, 2022	Never	144	VeriLog	-
Dijkstra	Feb 6th, 2022	Never	146	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	148	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	142	VeriLog	-
Untitled	Feb 5th, 2022	Never	148	VeriLog	-
Dijkstra rough	Feb 4th, 2022	Never	159	VeriLog	-
Untitled	Feb 4th, 2022	Never	139	VeriLog	-
Untitled	Feb 4th, 2022	Never	142	C++	-
Untitled	Feb 4th, 2022	Never	138	VeriLog	-
LED	Feb 1st, 2022	Never	137	VeriLog	-
LED	Feb 1st, 2022	Never	146	VeriLog	-
LED	Feb 1st, 2022	Never	118	None	-
LED_tb	Feb 1st, 2022	Never	129	VeriLog	-
Untitled	Jan 31st, 2022	Never	131	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	138	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	125	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	139	VeriLog	-
Untitled	Jan 31st, 2022	Never	119	None	-
Documented LSA	Jan 31st, 2022	Never	138	VeriLog	-