Sidsh's Pastebin

1,116 39,032 0 3 years ago

Name / Title	Added	Expires	Hits	Syntax
Untitled	Dec 4th, 2024	Never	6,629	SystemVerilog	-
Untitled	Dec 1st, 2024	Never	96	None	-
function cache rajni	Dec 1st, 2024	Never	846	SystemVerilog	-
Untitled	Nov 8th, 2024	Never	106	None	-
Untitled	Nov 2nd, 2022	Never	450	None	-
Reporting system	Oct 29th, 2022	Never	1,434	SystemVerilog	-
sequencer.sv	Oct 29th, 2022	Never	1,469	SystemVerilog	-
monitor.sv	Oct 29th, 2022	Never	1,542	SystemVerilog	-
driver.sv	Oct 29th, 2022	Never	1,516	SystemVerilog	-
interface.sv	Oct 29th, 2022	Never	1,391	SystemVerilog	-
sequence.sv	Oct 29th, 2022	Never	1,622	SystemVerilog	-
sequence_item.sv	Oct 29th, 2022	Never	1,568	SystemVerilog	-
agent.sv	Oct 29th, 2022	Never	1,427	SystemVerilog	-
env.sv	Oct 29th, 2022	Never	1,460	SystemVerilog	-
test.sv	Oct 29th, 2022	Never	1,385	SystemVerilog	-
top.sv	Oct 29th, 2022	Never	1,334	SystemVerilog	-
Haskell blinker.	Jun 26th, 2022	Never	524	Haskell	-
Haskell Blinker	Jun 26th, 2022	Never	252	None	-
Haskell Blinker	Jun 26th, 2022	Never	474	Haskell	-
Blinker Haskell;	Jun 26th, 2022	Never	398	Haskell	-
WB_pwmaudiocontroller	Apr 10th, 2022	Never	942	SystemVerilog	-
Counter	Mar 25th, 2022	Never	245	None	-
LSA Documented 2.0	Mar 3rd, 2022	Never	415	VeriLog	-
LED Documented (sec*) 2.0	Mar 3rd, 2022	Never	249	None	-
ADC Documented 2.0	Mar 3rd, 2022	Never	418	VeriLog	-
LSA Documented 1.1	Mar 3rd, 2022	Never	425	VeriLog	-
LED Documented (sec*)	Mar 3rd, 2022	Never	410	VeriLog	-
ADC Documented	Mar 3rd, 2022	Never	290	VeriLog	-
UART messages added to Pick and Place+e	Mar 3rd, 2022	Never	268	VeriLog	-
Untitled	Mar 3rd, 2022	Never	267	VeriLog	-
Electromagnet enabled LSA	Mar 1st, 2022	Never	311	VeriLog	-
SM Path+Dep 1.2	Mar 1st, 2022	Never	272	VeriLog	-
Path Traversal+Deposition SM	Feb 28th, 2022	Never	277	VeriLog	-
SM Path Traversal 1.1	Feb 28th, 2022	Never	278	VeriLog	-
Path Traversal SM	Feb 27th, 2022	Never	289	VeriLog	-
Dijkstra Sep	Feb 11th, 2022	Never	335	VeriLog	-
Dijkstra_only	Feb 11th, 2022	Never	243	VeriLog	-
LSA Backup	Feb 10th, 2022	Never	266	None	-
LSA Hardcoded	Feb 10th, 2022	Never	282	VeriLog	-
LSA Hardcoded TB	Feb 10th, 2022	Never	263	VeriLog	-
Hardcoded LSA	Feb 10th, 2022	Never	288	VeriLog	-
Untitled	Feb 9th, 2022	Never	273	VeriLog	-
Untitled	Feb 9th, 2022	Never	269	VeriLog	-
LSA+Dijkstra 2.0	Feb 9th, 2022	Never	274	VeriLog	-
Dijkstra+LSA	Feb 8th, 2022	Never	264	VeriLog	-
Dijkstra Reference	Feb 7th, 2022	Never	277	VeriLog	-
Dijkstra tb	Feb 6th, 2022	Never	275	VeriLog	-
Dijkstra	Feb 6th, 2022	Never	261	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	248	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	242	VeriLog	-
Untitled	Feb 5th, 2022	Never	263	VeriLog	-
Dijkstra rough	Feb 4th, 2022	Never	260	VeriLog	-
Untitled	Feb 4th, 2022	Never	244	VeriLog	-
Untitled	Feb 4th, 2022	Never	255	C++	-
Untitled	Feb 4th, 2022	Never	239	VeriLog	-
LED	Feb 1st, 2022	Never	248	VeriLog	-
LED	Feb 1st, 2022	Never	245	VeriLog	-
LED	Feb 1st, 2022	Never	227	None	-
LED_tb	Feb 1st, 2022	Never	238	VeriLog	-
Untitled	Jan 31st, 2022	Never	245	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	262	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	225	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	268	VeriLog	-
Untitled	Jan 31st, 2022	Never	219	None	-
Documented LSA	Jan 31st, 2022	Never	262	VeriLog	-