Sidsh's Pastebin

1,156 40,814 0 3 years ago

Name / Title	Added	Expires	Hits	Syntax
Untitled	Dec 4th, 2024	Never	6,777	SystemVerilog	-
Untitled	Dec 1st, 2024	Never	120	None	-
function cache rajni	Dec 1st, 2024	Never	989	SystemVerilog	-
Untitled	Nov 8th, 2024	Never	135	None	-
Untitled	Nov 2nd, 2022	Never	474	None	-
Reporting system	Oct 29th, 2022	Never	1,457	SystemVerilog	-
sequencer.sv	Oct 29th, 2022	Never	1,487	SystemVerilog	-
monitor.sv	Oct 29th, 2022	Never	1,565	SystemVerilog	-
driver.sv	Oct 29th, 2022	Never	1,537	SystemVerilog	-
interface.sv	Oct 29th, 2022	Never	1,411	SystemVerilog	-
sequence.sv	Oct 29th, 2022	Never	1,647	SystemVerilog	-
sequence_item.sv	Oct 29th, 2022	Never	1,587	SystemVerilog	-
agent.sv	Oct 29th, 2022	Never	1,458	SystemVerilog	-
env.sv	Oct 29th, 2022	Never	1,485	SystemVerilog	-
test.sv	Oct 29th, 2022	Never	1,409	SystemVerilog	-
top.sv	Oct 29th, 2022	Never	1,358	SystemVerilog	-
Haskell blinker.	Jun 26th, 2022	Never	547	Haskell	-
Haskell Blinker	Jun 26th, 2022	Never	273	None	-
Haskell Blinker	Jun 26th, 2022	Never	499	Haskell	-
Blinker Haskell;	Jun 26th, 2022	Never	428	Haskell	-
WB_pwmaudiocontroller	Apr 10th, 2022	Never	964	SystemVerilog	-
Counter	Mar 25th, 2022	Never	268	None	-
LSA Documented 2.0	Mar 3rd, 2022	Never	440	VeriLog	-
LED Documented (sec*) 2.0	Mar 3rd, 2022	Never	267	None	-
ADC Documented 2.0	Mar 3rd, 2022	Never	444	VeriLog	-
LSA Documented 1.1	Mar 3rd, 2022	Never	446	VeriLog	-
LED Documented (sec*)	Mar 3rd, 2022	Never	432	VeriLog	-
ADC Documented	Mar 3rd, 2022	Never	312	VeriLog	-
UART messages added to Pick and Place+e	Mar 3rd, 2022	Never	289	VeriLog	-
Untitled	Mar 3rd, 2022	Never	290	VeriLog	-
Electromagnet enabled LSA	Mar 1st, 2022	Never	342	VeriLog	-
SM Path+Dep 1.2	Mar 1st, 2022	Never	296	VeriLog	-
Path Traversal+Deposition SM	Feb 28th, 2022	Never	299	VeriLog	-
SM Path Traversal 1.1	Feb 28th, 2022	Never	302	VeriLog	-
Path Traversal SM	Feb 27th, 2022	Never	322	VeriLog	-
Dijkstra Sep	Feb 11th, 2022	Never	361	VeriLog	-
Dijkstra_only	Feb 11th, 2022	Never	269	VeriLog	-
LSA Backup	Feb 10th, 2022	Never	287	None	-
LSA Hardcoded	Feb 10th, 2022	Never	306	VeriLog	-
LSA Hardcoded TB	Feb 10th, 2022	Never	297	VeriLog	-
Hardcoded LSA	Feb 10th, 2022	Never	319	VeriLog	-
Untitled	Feb 9th, 2022	Never	291	VeriLog	-
Untitled	Feb 9th, 2022	Never	291	VeriLog	-
LSA+Dijkstra 2.0	Feb 9th, 2022	Never	306	VeriLog	-
Dijkstra+LSA	Feb 8th, 2022	Never	285	VeriLog	-
Dijkstra Reference	Feb 7th, 2022	Never	302	VeriLog	-
Dijkstra tb	Feb 6th, 2022	Never	289	VeriLog	-
Dijkstra	Feb 6th, 2022	Never	280	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	268	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	263	VeriLog	-
Untitled	Feb 5th, 2022	Never	285	VeriLog	-
Dijkstra rough	Feb 4th, 2022	Never	281	VeriLog	-
Untitled	Feb 4th, 2022	Never	261	VeriLog	-
Untitled	Feb 4th, 2022	Never	278	C++	-
Untitled	Feb 4th, 2022	Never	262	VeriLog	-
LED	Feb 1st, 2022	Never	272	VeriLog	-
LED	Feb 1st, 2022	Never	272	VeriLog	-
LED	Feb 1st, 2022	Never	248	None	-
LED_tb	Feb 1st, 2022	Never	258	VeriLog	-
Untitled	Jan 31st, 2022	Never	285	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	288	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	248	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	291	VeriLog	-
Untitled	Jan 31st, 2022	Never	239	None	-
Documented LSA	Jan 31st, 2022	Never	286	VeriLog	-