Sidsh's Pastebin

1,173 41,233 0 3 years ago

Name / Title	Added	Expires	Hits	Syntax
Untitled	Dec 4th, 2024	Never	6,820	SystemVerilog	-
Untitled	Dec 1st, 2024	Never	127	None	-
function cache rajni	Dec 1st, 2024	Never	1,027	SystemVerilog	-
Untitled	Nov 8th, 2024	Never	141	None	-
Untitled	Nov 2nd, 2022	Never	482	None	-
Reporting system	Oct 29th, 2022	Never	1,467	SystemVerilog	-
sequencer.sv	Oct 29th, 2022	Never	1,493	SystemVerilog	-
monitor.sv	Oct 29th, 2022	Never	1,575	SystemVerilog	-
driver.sv	Oct 29th, 2022	Never	1,543	SystemVerilog	-
interface.sv	Oct 29th, 2022	Never	1,423	SystemVerilog	-
sequence.sv	Oct 29th, 2022	Never	1,654	SystemVerilog	-
sequence_item.sv	Oct 29th, 2022	Never	1,597	SystemVerilog	-
agent.sv	Oct 29th, 2022	Never	1,466	SystemVerilog	-
env.sv	Oct 29th, 2022	Never	1,495	SystemVerilog	-
test.sv	Oct 29th, 2022	Never	1,418	SystemVerilog	-
top.sv	Oct 29th, 2022	Never	1,367	SystemVerilog	-
Haskell blinker.	Jun 26th, 2022	Never	551	Haskell	-
Haskell Blinker	Jun 26th, 2022	Never	277	None	-
Haskell Blinker	Jun 26th, 2022	Never	507	Haskell	-
Blinker Haskell;	Jun 26th, 2022	Never	440	Haskell	-
WB_pwmaudiocontroller	Apr 10th, 2022	Never	974	SystemVerilog	-
Counter	Mar 25th, 2022	Never	279	None	-
LSA Documented 2.0	Mar 3rd, 2022	Never	449	VeriLog	-
LED Documented (sec*) 2.0	Mar 3rd, 2022	Never	274	None	-
ADC Documented 2.0	Mar 3rd, 2022	Never	453	VeriLog	-
LSA Documented 1.1	Mar 3rd, 2022	Never	460	VeriLog	-
LED Documented (sec*)	Mar 3rd, 2022	Never	449	VeriLog	-
ADC Documented	Mar 3rd, 2022	Never	320	VeriLog	-
UART messages added to Pick and Place+e	Mar 3rd, 2022	Never	302	VeriLog	-
Untitled	Mar 3rd, 2022	Never	302	VeriLog	-
Electromagnet enabled LSA	Mar 1st, 2022	Never	355	VeriLog	-
SM Path+Dep 1.2	Mar 1st, 2022	Never	306	VeriLog	-
Path Traversal+Deposition SM	Feb 28th, 2022	Never	305	VeriLog	-
SM Path Traversal 1.1	Feb 28th, 2022	Never	313	VeriLog	-
Path Traversal SM	Feb 27th, 2022	Never	334	VeriLog	-
Dijkstra Sep	Feb 11th, 2022	Never	368	VeriLog	-
Dijkstra_only	Feb 11th, 2022	Never	283	VeriLog	-
LSA Backup	Feb 10th, 2022	Never	296	None	-
LSA Hardcoded	Feb 10th, 2022	Never	316	VeriLog	-
LSA Hardcoded TB	Feb 10th, 2022	Never	308	VeriLog	-
Hardcoded LSA	Feb 10th, 2022	Never	330	VeriLog	-
Untitled	Feb 9th, 2022	Never	304	VeriLog	-
Untitled	Feb 9th, 2022	Never	297	VeriLog	-
LSA+Dijkstra 2.0	Feb 9th, 2022	Never	314	VeriLog	-
Dijkstra+LSA	Feb 8th, 2022	Never	300	VeriLog	-
Dijkstra Reference	Feb 7th, 2022	Never	314	VeriLog	-
Dijkstra tb	Feb 6th, 2022	Never	298	VeriLog	-
Dijkstra	Feb 6th, 2022	Never	288	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	273	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	267	VeriLog	-
Untitled	Feb 5th, 2022	Never	291	VeriLog	-
Dijkstra rough	Feb 4th, 2022	Never	286	VeriLog	-
Untitled	Feb 4th, 2022	Never	266	VeriLog	-
Untitled	Feb 4th, 2022	Never	286	C++	-
Untitled	Feb 4th, 2022	Never	267	VeriLog	-
LED	Feb 1st, 2022	Never	280	VeriLog	-
LED	Feb 1st, 2022	Never	277	VeriLog	-
LED	Feb 1st, 2022	Never	252	None	-
LED_tb	Feb 1st, 2022	Never	266	VeriLog	-
Untitled	Jan 31st, 2022	Never	300	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	300	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	256	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	302	VeriLog	-
Untitled	Jan 31st, 2022	Never	244	None	-
Documented LSA	Jan 31st, 2022	Never	298	VeriLog	-