ADC Documented 2.0

/*

*Team Id:           SM#2349
*Author List:       (Premraj,Siddesh,Viraj,Siddharth)
*Filename:          ADC
*Theme:             Soil Monitoring Bot
*Input:             (clk_1, dout, reset)
*Output:                (adc_cs_n, din, adc_sck, S1, S2, S3)

*/
module ADC(
    input  clk_1,               //50 MHz clock                                   PIN_R8
    input  dout,                //digital output from ADC128S022 (serial 12-bit) PIN_A9
    input reset,
    output adc_cs_n,            //ADC128S022 Chip Select                         PIN_A10
    output din,                 //Ch. address input to ADC128S022 (serial)       PIN_B10
    output reg adc_sck,         //2.5 MHz ADC clock                              PIN_B14

    output S1,
    output S2,
    output S3
);

reg [8:0]d1 = 9'b111011101;   //register to store channel adresses
reg [1:0]din_r = 0;           //register to store current adress output

reg d5 = 0;                         //If line detected, value of d5 is high for sensor 1
reg d6 = 0;                         //If line detected, value of d6 is high for sensor 2
reg d7 = 0;                         //If line detected, value of d7 is high for sensor 3
reg [5:0]c = 0;

//---------Assigning chip select pin---------
assign adc_cs_n = 0;

//---------Scale the clock from 50 to 2.5 MHz---------

always @(negedge clk_1)begin

    if(reset == 0)
     begin
        c <= 0;
     end
    else
    begin
        if(c == 47)begin
        c <= 0;
        end else begin
        c <= c + 1;
        end
    end

    if(reset == 0)
     begin
        din_r <= 0;
     end

    case(c)                                 //To store channel address
    1:din_r <= d1[0];
    2:din_r <= d1[1];
    3:din_r <= d1[2];

    17:din_r <= d1[3];
    18:din_r <= d1[4];
    19:din_r <= d1[5];

    33:din_r <= d1[6];
    34:din_r <= d1[7];
    35:din_r <= d1[8];
    default din_r <= 0;
    endcase

end

assign din = din_r;


always @(posedge clk_1)begin

    if(reset == 0)
     begin
        d5 <= 0;            //Resetting value of d5
        d6 <= 0;                //Resetting value of d6
        d7 <= 0;                //Resetting value of d7

     end

    case(c)                 //if threshold value >2000, one assigned channel bit will be high. And the line will be detected
    4:d7 <= dout;           //assigning value of dout to d7

    20:d5 <= dout;          //assigning value of dout to d5

    36:d6 <= dout;          //assigning value of dout to d6

    endcase

end

assign data_frame = c;

assign S1 = d5;
assign S2 = d6;
assign S3 = d7;


endmodule