driver.sv

class our_driver extends uvm_driver #(our_packet)       //Parameterized the driver class
    `uvm_component_utils(our_driver)

    our_interface intf;     //instantiating our interface
    our_packet pkt;         //instantiating our packet class

    //build phase
    //build other components
        uvm_config_db #(virtual our_interface) :: get (null, " * ", "intf", intf);      //The GET method

        pkt = our_packet :: type_id :: create ("Our Packet")        //created an object Our Packet

    //run phase
    task run_phase (uvm_pahse phase);

        forever begin
            @(posedge intf.clk)         //very similar to always block, intf.clk because we are using interface clock(external)

                seq_item_port.get_next_item(pkt);   //means 'from sequence item port get next item(packet pkt)'
                intf.input_1 <= pkt.input_1;        //means get input_1 from packet, and assign to the interfaces input_1
                seq_item_port.item_done();          //this tells that driver has given one packet and it is ready to accept next packet
end
endtask