| Name / Title | Added | Expires | Hits | Comments | Syntax | |
|---|---|---|---|---|---|---|
| SVV - Cucumber lab | Nov 26th, 2024 | Never | 383 | 0 | Java | - |
| LSIC - all labs so far in Verilog | Nov 25th, 2024 | Never | 1,206 | 0 | VeriLog | - |
| LSIC - Frequency Divider | Nov 25th, 2024 | Never | 1,153 | 0 | SystemVerilog | - |
| LSIC - 7 segment displays | Nov 25th, 2024 | Never | 1,197 | 0 | SystemVerilog | - |
| LSIC - Main System | Nov 25th, 2024 | Never | 1,100 | 0 | SystemVerilog | - |
| prj.tcl (LSIC lab) | Nov 19th, 2024 | Never | 208 | 0 | None | - |
| TimeMeasurement module (LSIC) | Nov 19th, 2024 | Never | 1,211 | 0 | VeriLog | - |
| cet_Test1_reqs | Nov 5th, 2024 | Never | 186 | 0 | None | - |
| DSP lab9 part2 | Apr 22nd, 2021 | Never | 1,267 | 0 | MatLab | - |
| CORDIC method | Dec 5th, 2019 | Never | 400 | 0 | C | - |
| frogs_lakes_WIP_Calin | Dec 4th, 2019 | Never | 412 | 0 | C | - |
| reg_file_16x32 | Nov 7th, 2019 | Never | 661 | 0 | VeriLog | - |
| bvd_to_e3_conv | Nov 7th, 2019 | Never | 691 | 0 | VeriLog | - |
| convo (needs fixing) | Jun 4th, 2019 | Never | 428 | 0 | C | - |
| first convolution v1.1 (notepad++ indentation) | Apr 15th, 2019 | Never | 420 | 0 | C | - |
| C Chess v0.12 | Mar 25th, 2019 | Never | 452 | 0 | C | - |
| sorting and searching | Mar 17th, 2019 | Never | 408 | 0 | C | - |
| unions, structs and bit fields | Mar 12th, 2019 | Never | 404 | 0 | C | - |