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dec_4s
regzarr
Nov 7th, 2019
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VeriLog
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module
dec_4s
(
input
[
3
:
0
]
s
,
input
we
,
output
[
15
:
0
]
o
)
;
assign
o
=
we
?
(
1
6'd1
<<
s
)
:
1
6'd0
;
endmodule
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