reg

module rgst # (
  parameter w = 8,
  parameter iv = { w { 1'b0} } )
  ( input [w-1 : 0] d,
    input clk, rst_b, clr, ld,
    output reg [w-1 : 0] q );

always @ (posedge clk, negedge rst_b) begin
  if (!rst_b || clr)
    q <= iv;
  else if (ld)
    q <= d;
  end
endmodule