reg_file_16x32

module reg_file_16x32(
  input [31:0] d,
  input [3:0] s,
  input we, clk, rst_b, clr,
  output [511:0] blk
  );

  wire [15:0]wires;
  dec_4s decoder(.s(s), .we(we), .o(wires));



  generate
    genvar i;
    for(i = 0; i < 16; i = i + 1) begin: vect
      rgst register(.d(d), .ld(wires[i]), .clk(clk), .rst_b(rst_b), .clr(clr),
                    .q(blk[(i+1)*32 - 1 : i*32]));
    end
  endgenerate

endmodule