LIBRARY IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Rejestr is
	Port(clk: in std_logic;
		  reset: in std_logic;
		  DI: in signed (15 downto 0);
		  BA: in signed (15 downto 0);
		  Sbb: in signed (3 downto 0);
		  Sbc: in signed (3 downto 0);
		  Sba: in signed (3 downto 0);
		  Sid: in signed (2 downto 0);
		  Sa: in signed (2 downto 0);
		  BB: out signed (15 downto 0);
		  BC: out signed (15 downto 0);
		  ADR: out signed (31 downto 0);
		  IRout: out signed (15 downto 0)
		  );

end entity;


architecture behv of Rejestr is
component ALU is
	port(	A1 : in std_logic_vector (15 downto 0);
			B1 : in std_logic_vector (15 downto 0);
			Salu: in std_logic_vector (3 downto 0);
			Y : out std_logic_vector (15 downto 0);
			P : out std_logic;
			C1 : out std_logic;
			Z : out std_logic;
			S : out std_logic;

			BBA : out std_logic_vector (15 downto 0);
			SSS : out std_logic_vector (15 downto 0)
		);
	end component;
	signal TMPBA: std_logic_vector (15 downto 0);
	signal TMPBB: std_logic_vector (15 downto 0);
	signal TMPBC: std_logic_vector (15 downto 0);

	BEGIN
	TMPBB <= BB;
	TMPBC <= BC;



	begin
	process (A1, B1, Salu)
		variable temp, AA, BB, CC : std_logic_vector (16 downto 0);
		variable CF, ZF, SF, PF, NF: out std_logic;

		begin
		A1 := TMPBB;
		B1 := TMPBC;
		AA(16) := A1(15);
		AA(15 downto 0) := A1;
		BB(16) := B1(15);
		BB(15 downto 0) := B1;
		CC(0) := CF;
		CC(16 downto 1) := "000000000000000";

		case Salu is
			when "0000" => temp := AA;
			when "0001" => temp := BB;
         when "0010" => temp := AA + BB;
			when "0011" => temp := AA - BB;
			when "0100" => temp := AA xnor BB;
         when "0101" => temp := AA + 1;
			when "0110" => temp := BB + 1;
			when "0111" => temp := not AA;
			when "1000" => temp := not BB;
			when "1001" => temp := AA and BB;
			when "1010" => temp := AA or BB;
			when "1011" => temp := AA xor BB;
			when "1100" => temp := AA + BB + CC;
			when "1101" =>	temp := AA - BB - CC;
			when "1110" => temp(16)  := AA(16);
								temp(15 downto 0) := AA(15 downto 0);
			when "1111" => temp(0) := '0' ;
								temp(16 downto 1) := AA(16 downto 1);
         when others => temp:= null;
		end case;

		test_par(temp(15 downto 0), PF, NF);

		if(temp = "0000000000000000") then
			ZF := '1';
		else
			ZF := '0';
		end if;

		if(temp(15) = '1') then
			SF := '1';
		else
			SF := '0';
		end if;

		CF := temp(16) xor temp(15);

		Y <= temp(15 downto 0);
      Z <= ZF;
      S <= SF;
      C1 <= CF;
      P <= PF;
		tmpToHex <= tmp;


		begin
			mapp = port map (TMPBA <= Y);
	end process;


	BA := TMPBA;


	begin
	process(clk,Sbb,Sbc, Sba, Sa,DI)
	variable AP: signed (31 downto 0);
	variable IR, TMP, A, B, C, D, E, F: signed (15 downto 0);
	variable PC, SP, AD, ATMP: signed (31 downto 0);
	begin
	if(clk = '1') then
		if(reset = '1') then
			IR :=  "0000000000000001";
			TMP := "0000000000000010";
			A :=   "0000000000000011";
			B :=   "0000000000000100";
			C :=   "0000000000000101";
			D :=   "0000000000000110";
			E :=   "0000000000000111";
			F :=   "0000000000001000";
			AD :=  "00000000000000000000000000001001";
			PC :=  "00000000000000000000000000001010";
			SP :=  "00000000000000000000000000001011" ;
			ATMP := "00000000000000000000000000001100" ;
	end if;

	case Sid is
		when "001" => PC := PC+1;
		when "010" => SP := SP+1;
		when "011" => SP := SP-1;
		when "100" => AD := AD+1;
		when "101" => AD := AD-1;
		when others => NULL;
	end case;
	end if;
	case Sba is
		when "0000" => IR := BA;
		when "0001" => TMP := BA;
		when "0010" => A := BA;
		when "0011" => B := BA;
		when "0100" => C := BA;
		when "0101" => D := BA;
		when "0110" => E := BA;
		when "0111" => F := BA;
		when "1000" => AD(15 downto 0) := BA;
		when "1001" => AD(31 downto 16) := BA;
		when "1010" => PC(15 downto 0) := BA;
		when "1011" => PC(31 downto 16) := BA;
		when "1100" => SP(15 downto 0) := BA;
		when "1101" => SP(31 downto 16) := BA;
		when "1110" => ATMP(15 downto 0) := BA;
		when "1111" => ATMP(31 downto 16) := BA;
	end case;

	case Sbb is
		when "0000" => BB <= DI;
		when "0001" => BB <= TMP;
		when "0010" => BB <= A;
		when "0011" => BB <= B;
		when "0100" => BB <= C;
		when "0101" => BB <= D;
		when "0110" => BB <= E;
		when "0111" => BB <= F;
		when "1000" => BB <= AD(15 downto 0);
		when "1001" => BB <= AD(31 downto 16);
		when "1010" => BB <= PC(15 downto 0);
		when "1011" => BB <= PC(31 downto 16);
		when "1100" => BB <= SP(15 downto 0);
		when "1101" => BB <= SP(31 downto 16);
		when "1110" => BB <= ATMP(15 downto 0);
		when "1111" => BB <= ATMP(31 downto 16);
		when others => NULL;
	end case;

	case Sbc is
		when "0000" => BC <= DI;
		when "0001" => BC <= TMP;
		when "0010" => BC <= A;
		when "0011" => BC <= B;
		when "0100" => BC <= C;
		when "0101" => BC <= D;
		when "0110" => BC <= E;
		when "0111" => BC <= F;
		when "1000" => BC <= AD(15 downto 0);
		when "1001" => BC <= AD(31 downto 16);
		when "1010" => BC <= PC(15 downto 0);
		when "1011" => BC <= PC(31 downto 16);
		when "1100" => BC <= SP(15 downto 0);
		when "1101" => BC <= SP(31 downto 16);
		when "1110" => BC <= ATMP(15 downto 0);
		when "1111" => BC <= ATMP(31 downto 16);
		when others => NULL;
	end case;

	case Sa is
		when "000" => ADR<= AD;
		when "001" => ADR<= PC;
		when "010" => ADR<= SP;
		when "011" => ADR<= ATMP;
		when others => NULL;
	end case;
	IR := PC (15 downto 0);
	IRout <= IR;
end process;
end behv;