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- LIBRARY ieee;
- use ieee.std_logic_1164.all;
- entity alivhd is
- port(A,B:in std_logic_vector (1 downto 0);
- resultat:out std_logic_vector (7 downto 1));
- end alivhd;
- architecture ALI of alivhd is
- begin
- resultat(1)<='1';
- resultat(2)<='1';
- resultat(3)<=(NOT(A(1))AND(NOT(A(0))))OR(NOT(A(1))AND(B(0)))OR(NOT(A(1))AND(B(1)))OR((B(1))AND(B(0)))OR(NOT(A(0))AND(B(1)));
- resultat(4)<='0';
- resultat(5)<=((A(1))AND(NOT(B(1))))OR((A(0))AND(NOT(B(1))))OR((NOT(B(1)))AND(NOT(B(0))))OR((A(1))AND(A(0)))OR((A(1))AND(NOT(B(0))));
- resultat(6)<='1';
- resultat(7)<='0';
- end ALI;
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