Artentus

Artentus's Pastebin

1,800 23,387 0 7 years ago
Name / Title Added Expires Hits Comments Syntax  
CustomASM: 32 Bit ISA Nov 30th, 2021 Never 373 0 None -
Byte addressing logic Nov 30th, 2021 Never 1,323 0 VeriLog -
32 bit ISA Nov 17th, 2021 Never 96 0 None -
16 Bit ISA Sep 7th, 2021 Never 180 0 None -
Rail Segments 2.0 Extras May 16th, 2019 Never 770 0 None -
2/4-Lane Compatibility Rail Segments 2.0 May 16th, 2019 Never 534 0 None -
2-Lane Rail Segments 2.0 May 16th, 2019 Never 678 0 None -
4-Lane Rail Segments 2.0 May 16th, 2019 Never 818 0 None -
Early Game Expensive Green Circuit Design Nov 13th, 2018 Never 206 0 None -
4-to-2-Lane Rail Segments May 16th, 2017 Never 4,453 0 None -
2-Lane Rail Segments May 16th, 2017 Never 7,293 0 None -
4-Lane Rail Segments May 16th, 2017 Never 6,665 0 None -