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- module RamModeDecoder
- (
- input [ 1:0] addr,
- input [31:0] data_in,
- input [ 1:0] mem_mode,
- output reg [31:0] data_out
- );
- localparam
- MEM_MODE_32 = 2'b00,
- MEM_MODE_8 = 2'b01,
- MEM_MODE_16 = 2'b10;
- always @(*) begin
- case (mem_mode)
- MEM_MODE_8: begin
- data_out[31:8] = 24'h0;
- case (addr)
- 2'b00: data_out[7:0] = data_in[ 7: 0];
- 2'b01: data_out[7:0] = data_in[15: 8];
- 2'b10: data_out[7:0] = data_in[23:16];
- 2'b11: data_out[7:0] = data_in[31:24];
- endcase
- end
- MEM_MODE_16: begin
- data_out[31:16] = 16'h0;
- if (addr[1]) begin
- data_out[15:0] = data_in[31:16];
- end else begin
- data_out[15:0] = data_in[15:0];
- end
- end
- MEM_MODE_32: data_out = data_in;
- default: data_out = 32'h0;
- endcase
- end
- endmodule
- module RamModeEncoder
- (
- input [ 1:0] addr,
- input [31:0] data_in,
- input [ 1:0] mem_mode,
- output reg [31:0] data_out,
- output reg b0, b1, b2, b3
- );
- localparam
- MEM_MODE_32 = 2'b00,
- MEM_MODE_8 = 2'b01,
- MEM_MODE_16 = 2'b10;
- always @(*) begin
- case (mem_mode)
- MEM_MODE_8: begin
- case (addr)
- 2'b00: begin
- data_out[ 7: 0] = data_in[7:0];
- data_out[31: 8] = 24'h0;
- b0 = 1'b1;
- b1 = 1'b0;
- b2 = 1'b0;
- b3 = 1'b0;
- end
- 2'b01: begin
- data_out[15: 8] = data_in[7:0];
- data_out[ 7: 0] = 8'h0;
- data_out[31:16] = 16'h0;
- b0 = 1'b0;
- b1 = 1'b1;
- b2 = 1'b0;
- b3 = 1'b0;
- end
- 2'b10: begin
- data_out[23:16] = data_in[7:0];
- data_out[15: 0] = 16'h0;
- data_out[31:24] = 8'h0;
- b0 = 1'b0;
- b1 = 1'b0;
- b2 = 1'b1;
- b3 = 1'b0;
- end
- 2'b11: begin
- data_out[31:24] = data_in[7:0];
- data_out[23: 0] = 24'h0;
- b0 = 1'b0;
- b1 = 1'b0;
- b2 = 1'b0;
- b3 = 1'b1;
- end
- endcase
- end
- MEM_MODE_16: begin
- if (addr[1]) begin
- data_out[31:16] = data_in[15:0];
- data_out[15: 0] = 16'h0;
- b0 = 1'b0;
- b1 = 1'b0;
- b2 = 1'b1;
- b3 = 1'b1;
- end else begin
- data_out[15: 0] = data_in[15:0];
- data_out[31:16] = 16'h0;
- b0 = 1'b1;
- b1 = 1'b1;
- b2 = 1'b0;
- b3 = 1'b0;
- end
- end
- MEM_MODE_32: begin
- data_out = data_in;
- b0 = 1'b1;
- b1 = 1'b1;
- b2 = 1'b1;
- b3 = 1'b1;
- end
- default: begin
- data_out = 32'h0;
- b0 = 1'b0;
- b1 = 1'b0;
- b2 = 1'b0;
- b3 = 1'b0;
- end
- endcase
- end
- endmodule
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