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Artentus

CustomASM: 32 Bit ISA

Artentus
Nov 30th, 2021 (edited)
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  1. #bits 8
  2.  
  3. #subruledef reg
  4. {
  5. r{i: u5} => i
  6. zero => 0`5
  7. ra => 1`5
  8. bp => 2`5
  9. sp => 3`5
  10. a{i: u3} => (i`5 + 4)`5
  11. t{i: u5} => {
  12. assert(i < 10)
  13. (i + 12)`5
  14. }
  15. s{i: u5} => {
  16. assert(i < 10)
  17. (i + 22)`5
  18. }
  19. }
  20.  
  21. #subruledef imm
  22. {
  23. {v: i32} => {
  24. assert((v < 8192) && (v >= -8192))
  25. 0b0 @ v`14
  26. }
  27. {v: i32} => {
  28. assert((v >= 8192) || (v < -8192))
  29. 0`14 @ (v >> 14)`18 @ 0b1 @ v`14
  30. }
  31. }
  32.  
  33. #subruledef rel
  34. {
  35. {v: i32} => {
  36. offset = v - $ - 4
  37. assert((offset < 8192) && (offset >= -8192))
  38. 0b0 @ offset`14
  39. }
  40. {v: i32} => {
  41. offset = v - $ - 4
  42. assert((offset >= 8192) || (offset < -8192))
  43. 0`14 @ (offset >> 14)`18 @ 0b1 @ offset`14
  44. }
  45. }
  46.  
  47. ; real instructions
  48. #ruledef
  49. {
  50. NOP => le(0`10 @ 0`5 @ 0`5 @ 0`5 @ 0x0 @ 0b000)
  51. BRK => le(0`10 @ 0`5 @ 0`5 @ 0`5 @ 0x1 @ 0b000)
  52. HLT => le(0`10 @ 0`5 @ 0`5 @ 0`5 @ 0x2 @ 0b000)
  53. ERR => le(0`10 @ 0`5 @ 0`5 @ 0`5 @ 0x3 @ 0b000)
  54.  
  55. ADD {d: reg}, {l: reg}, {r: reg} => le(0`10 @ {r} @ {l} @ {d} @ 0x1 @ 0b001)
  56. ADDC {d: reg}, {l: reg}, {r: reg} => le(0`10 @ {r} @ {l} @ {d} @ 0x2 @ 0b001)
  57. SUB {d: reg}, {l: reg}, {r: reg} => le(0`10 @ {r} @ {l} @ {d} @ 0x3 @ 0b001)
  58. SUBB {d: reg}, {l: reg}, {r: reg} => le(0`10 @ {r} @ {l} @ {d} @ 0x4 @ 0b001)
  59. AND {d: reg}, {l: reg}, {r: reg} => le(0`10 @ {r} @ {l} @ {d} @ 0x5 @ 0b001)
  60. OR {d: reg}, {l: reg}, {r: reg} => le(0`10 @ {r} @ {l} @ {d} @ 0x6 @ 0b001)
  61. XOR {d: reg}, {l: reg}, {r: reg} => le(0`10 @ {r} @ {l} @ {d} @ 0x7 @ 0b001)
  62. SHL {d: reg}, {l: reg}, {r: reg} => le(0`10 @ {r} @ {l} @ {d} @ 0x8 @ 0b001)
  63. ASR {d: reg}, {l: reg}, {r: reg} => le(0`10 @ {r} @ {l} @ {d} @ 0x9 @ 0b001)
  64. LSR {d: reg}, {l: reg}, {r: reg} => le(0`10 @ {r} @ {l} @ {d} @ 0xA @ 0b001)
  65.  
  66. ADD {d: reg}, {l: reg}, {v: imm} => le({v} @ {l} @ {d} @ 0x1 @ 0b010)
  67. ADDC {d: reg}, {l: reg}, {v: imm} => le({v} @ {l} @ {d} @ 0x2 @ 0b010)
  68. SUB {d: reg}, {l: reg}, {v: imm} => le({v} @ {l} @ {d} @ 0x3 @ 0b010)
  69. SUBB {d: reg}, {l: reg}, {v: imm} => le({v} @ {l} @ {d} @ 0x4 @ 0b010)
  70. AND {d: reg}, {l: reg}, {v: imm} => le({v} @ {l} @ {d} @ 0x5 @ 0b010)
  71. OR {d: reg}, {l: reg}, {v: imm} => le({v} @ {l} @ {d} @ 0x6 @ 0b010)
  72. XOR {d: reg}, {l: reg}, {v: imm} => le({v} @ {l} @ {d} @ 0x7 @ 0b010)
  73. SHL {d: reg}, {l: reg}, {v: imm} => le({v} @ {l} @ {d} @ 0x8 @ 0b010)
  74. ASR {d: reg}, {l: reg}, {v: imm} => le({v} @ {l} @ {d} @ 0x9 @ 0b010)
  75. LSR {d: reg}, {l: reg}, {v: imm} => le({v} @ {l} @ {d} @ 0xA @ 0b010)
  76.  
  77. ADD {d: reg}, {v: imm}, {r: reg} => le({v} @ {r} @ {d} @ 0x1 @ 0b011)
  78. ADDC {d: reg}, {v: imm}, {r: reg} => le({v} @ {r} @ {d} @ 0x2 @ 0b011)
  79. SUB {d: reg}, {v: imm}, {r: reg} => le({v} @ {r} @ {d} @ 0x3 @ 0b011)
  80. SUBB {d: reg}, {v: imm}, {r: reg} => le({v} @ {r} @ {d} @ 0x4 @ 0b011)
  81. AND {d: reg}, {v: imm}, {r: reg} => le({v} @ {r} @ {d} @ 0x5 @ 0b011)
  82. OR {d: reg}, {v: imm}, {r: reg} => le({v} @ {r} @ {d} @ 0x6 @ 0b011)
  83. XOR {d: reg}, {v: imm}, {r: reg} => le({v} @ {r} @ {d} @ 0x7 @ 0b011)
  84. SHL {d: reg}, {v: imm}, {r: reg} => le({v} @ {r} @ {d} @ 0x8 @ 0b011)
  85. ASR {d: reg}, {v: imm}, {r: reg} => le({v} @ {r} @ {d} @ 0x9 @ 0b011)
  86. LSR {d: reg}, {v: imm}, {r: reg} => le({v} @ {r} @ {d} @ 0xA @ 0b011)
  87.  
  88. LD {d: reg}, [{s: reg} + {o: reg}] => le(0`10 @ {o} @ {s} @ {d} @ 0x0 @ 0b100)
  89. LD {d: reg}, [{s: reg} + {v: imm}] => le( {v} @ {s} @ {d} @ 0x1 @ 0b100)
  90. ST [{d: reg} + {o: reg}], {s: reg} => le(0`10 @ {o} @ {s} @ {d} @ 0x2 @ 0b100)
  91. ST [{d: reg} + {v: imm}], {s: reg} => le( {v} @ {s} @ {d} @ 0x3 @ 0b100)
  92. LD8 {d: reg}, [{s: reg} + {o: reg}] => le(0`10 @ {o} @ {s} @ {d} @ 0x4 @ 0b100)
  93. LD8 {d: reg}, [{s: reg} + {v: imm}] => le( {v} @ {s} @ {d} @ 0x5 @ 0b100)
  94. ST8 [{d: reg} + {o: reg}], {s: reg} => le(0`10 @ {o} @ {s} @ {d} @ 0x6 @ 0b100)
  95. ST8 [{d: reg} + {v: imm}], {s: reg} => le( {v} @ {s} @ {d} @ 0x7 @ 0b100)
  96. LD16 {d: reg}, [{s: reg} + {o: reg}] => le(0`10 @ {o} @ {s} @ {d} @ 0x8 @ 0b100)
  97. LD16 {d: reg}, [{s: reg} + {v: imm}] => le( {v} @ {s} @ {d} @ 0x9 @ 0b100)
  98. ST16 [{d: reg} + {o: reg}], {s: reg} => le(0`10 @ {o} @ {s} @ {d} @ 0xA @ 0b100)
  99. ST16 [{d: reg} + {v: imm}], {s: reg} => le( {v} @ {s} @ {d} @ 0xB @ 0b100)
  100.  
  101. JP.C {s: reg} + {o: reg} => le(0`10 @ {o} @ {s} @ 0`5 @ 0x1 @ 0b101)
  102. JP.Z {s: reg} + {o: reg} => le(0`10 @ {o} @ {s} @ 0`5 @ 0x2 @ 0b101)
  103. JP.S {s: reg} + {o: reg} => le(0`10 @ {o} @ {s} @ 0`5 @ 0x3 @ 0b101)
  104. JP.O {s: reg} + {o: reg} => le(0`10 @ {o} @ {s} @ 0`5 @ 0x4 @ 0b101)
  105. JP.NC {s: reg} + {o: reg} => le(0`10 @ {o} @ {s} @ 0`5 @ 0x5 @ 0b101)
  106. JP.NZ {s: reg} + {o: reg} => le(0`10 @ {o} @ {s} @ 0`5 @ 0x6 @ 0b101)
  107. JP.NS {s: reg} + {o: reg} => le(0`10 @ {o} @ {s} @ 0`5 @ 0x7 @ 0b101)
  108. JP.NO {s: reg} + {o: reg} => le(0`10 @ {o} @ {s} @ 0`5 @ 0x8 @ 0b101)
  109. JP.U.LE {s: reg} + {o: reg} => le(0`10 @ {o} @ {s} @ 0`5 @ 0x9 @ 0b101)
  110. JP.U.G {s: reg} + {o: reg} => le(0`10 @ {o} @ {s} @ 0`5 @ 0xA @ 0b101)
  111. JP.S.L {s: reg} + {o: reg} => le(0`10 @ {o} @ {s} @ 0`5 @ 0xB @ 0b101)
  112. JP.S.GE {s: reg} + {o: reg} => le(0`10 @ {o} @ {s} @ 0`5 @ 0xC @ 0b101)
  113. JP.S.LE {s: reg} + {o: reg} => le(0`10 @ {o} @ {s} @ 0`5 @ 0xD @ 0b101)
  114. JP.S.G {s: reg} + {o: reg} => le(0`10 @ {o} @ {s} @ 0`5 @ 0xE @ 0b101)
  115. JMP {s: reg} + {o: reg} => le(0`10 @ {o} @ {s} @ 0`5 @ 0xF @ 0b101)
  116.  
  117. JP.C [{s: reg} + {o: reg}] => le(0`10 @ {o} @ {s} @ 1`5 @ 0x1 @ 0b101)
  118. JP.Z [{s: reg} + {o: reg}] => le(0`10 @ {o} @ {s} @ 1`5 @ 0x2 @ 0b101)
  119. JP.S [{s: reg} + {o: reg}] => le(0`10 @ {o} @ {s} @ 1`5 @ 0x3 @ 0b101)
  120. JP.O [{s: reg} + {o: reg}] => le(0`10 @ {o} @ {s} @ 1`5 @ 0x4 @ 0b101)
  121. JP.NC [{s: reg} + {o: reg}] => le(0`10 @ {o} @ {s} @ 1`5 @ 0x5 @ 0b101)
  122. JP.NZ [{s: reg} + {o: reg}] => le(0`10 @ {o} @ {s} @ 1`5 @ 0x6 @ 0b101)
  123. JP.NS [{s: reg} + {o: reg}] => le(0`10 @ {o} @ {s} @ 1`5 @ 0x7 @ 0b101)
  124. JP.NO [{s: reg} + {o: reg}] => le(0`10 @ {o} @ {s} @ 1`5 @ 0x8 @ 0b101)
  125. JP.U.LE [{s: reg} + {o: reg}] => le(0`10 @ {o} @ {s} @ 1`5 @ 0x9 @ 0b101)
  126. JP.U.G [{s: reg} + {o: reg}] => le(0`10 @ {o} @ {s} @ 1`5 @ 0xA @ 0b101)
  127. JP.S.L [{s: reg} + {o: reg}] => le(0`10 @ {o} @ {s} @ 1`5 @ 0xB @ 0b101)
  128. JP.S.GE [{s: reg} + {o: reg}] => le(0`10 @ {o} @ {s} @ 1`5 @ 0xC @ 0b101)
  129. JP.S.LE [{s: reg} + {o: reg}] => le(0`10 @ {o} @ {s} @ 1`5 @ 0xD @ 0b101)
  130. JP.S.G [{s: reg} + {o: reg}] => le(0`10 @ {o} @ {s} @ 1`5 @ 0xE @ 0b101)
  131. JMP [{s: reg} + {o: reg}] => le(0`10 @ {o} @ {s} @ 1`5 @ 0xF @ 0b101)
  132.  
  133. JP.C {s: reg} + {v: imm} => le({v} @ {s} @ 2`5 @ 0x1 @ 0b101)
  134. JP.Z {s: reg} + {v: imm} => le({v} @ {s} @ 2`5 @ 0x2 @ 0b101)
  135. JP.S {s: reg} + {v: imm} => le({v} @ {s} @ 2`5 @ 0x3 @ 0b101)
  136. JP.O {s: reg} + {v: imm} => le({v} @ {s} @ 2`5 @ 0x4 @ 0b101)
  137. JP.NC {s: reg} + {v: imm} => le({v} @ {s} @ 2`5 @ 0x5 @ 0b101)
  138. JP.NZ {s: reg} + {v: imm} => le({v} @ {s} @ 2`5 @ 0x6 @ 0b101)
  139. JP.NS {s: reg} + {v: imm} => le({v} @ {s} @ 2`5 @ 0x7 @ 0b101)
  140. JP.NO {s: reg} + {v: imm} => le({v} @ {s} @ 2`5 @ 0x8 @ 0b101)
  141. JP.U.LE {s: reg} + {v: imm} => le({v} @ {s} @ 2`5 @ 0x9 @ 0b101)
  142. JP.U.G {s: reg} + {v: imm} => le({v} @ {s} @ 2`5 @ 0xA @ 0b101)
  143. JP.S.L {s: reg} + {v: imm} => le({v} @ {s} @ 2`5 @ 0xB @ 0b101)
  144. JP.S.GE {s: reg} + {v: imm} => le({v} @ {s} @ 2`5 @ 0xC @ 0b101)
  145. JP.S.LE {s: reg} + {v: imm} => le({v} @ {s} @ 2`5 @ 0xD @ 0b101)
  146. JP.S.G {s: reg} + {v: imm} => le({v} @ {s} @ 2`5 @ 0xE @ 0b101)
  147. JMP {s: reg} + {v: imm} => le({v} @ {s} @ 2`5 @ 0xF @ 0b101)
  148.  
  149. JP.C [{s: reg} + {v: imm}] => le({v} @ {s} @ 3`5 @ 0x1 @ 0b101)
  150. JP.Z [{s: reg} + {v: imm}] => le({v} @ {s} @ 3`5 @ 0x2 @ 0b101)
  151. JP.S [{s: reg} + {v: imm}] => le({v} @ {s} @ 3`5 @ 0x3 @ 0b101)
  152. JP.O [{s: reg} + {v: imm}] => le({v} @ {s} @ 3`5 @ 0x4 @ 0b101)
  153. JP.NC [{s: reg} + {v: imm}] => le({v} @ {s} @ 3`5 @ 0x5 @ 0b101)
  154. JP.NZ [{s: reg} + {v: imm}] => le({v} @ {s} @ 3`5 @ 0x6 @ 0b101)
  155. JP.NS [{s: reg} + {v: imm}] => le({v} @ {s} @ 3`5 @ 0x7 @ 0b101)
  156. JP.NO [{s: reg} + {v: imm}] => le({v} @ {s} @ 3`5 @ 0x8 @ 0b101)
  157. JP.U.LE [{s: reg} + {v: imm}] => le({v} @ {s} @ 3`5 @ 0x9 @ 0b101)
  158. JP.U.G [{s: reg} + {v: imm}] => le({v} @ {s} @ 3`5 @ 0xA @ 0b101)
  159. JP.S.L [{s: reg} + {v: imm}] => le({v} @ {s} @ 3`5 @ 0xB @ 0b101)
  160. JP.S.GE [{s: reg} + {v: imm}] => le({v} @ {s} @ 3`5 @ 0xC @ 0b101)
  161. JP.S.LE [{s: reg} + {v: imm}] => le({v} @ {s} @ 3`5 @ 0xD @ 0b101)
  162. JP.S.G [{s: reg} + {v: imm}] => le({v} @ {s} @ 3`5 @ 0xE @ 0b101)
  163. JMP [{s: reg} + {v: imm}] => le({v} @ {s} @ 3`5 @ 0xF @ 0b101)
  164.  
  165. BR.C {v: rel} => le({v} @ 0`5 @ 4`5 @ 0x1 @ 0b101)
  166. BR.Z {v: rel} => le({v} @ 0`5 @ 4`5 @ 0x2 @ 0b101)
  167. BR.S {v: rel} => le({v} @ 0`5 @ 4`5 @ 0x3 @ 0b101)
  168. BR.O {v: rel} => le({v} @ 0`5 @ 4`5 @ 0x4 @ 0b101)
  169. BR.NC {v: rel} => le({v} @ 0`5 @ 4`5 @ 0x5 @ 0b101)
  170. BR.NZ {v: rel} => le({v} @ 0`5 @ 4`5 @ 0x6 @ 0b101)
  171. BR.NS {v: rel} => le({v} @ 0`5 @ 4`5 @ 0x7 @ 0b101)
  172. BR.NO {v: rel} => le({v} @ 0`5 @ 4`5 @ 0x8 @ 0b101)
  173. BR.U.LE {v: rel} => le({v} @ 0`5 @ 4`5 @ 0x9 @ 0b101)
  174. BR.U.G {v: rel} => le({v} @ 0`5 @ 4`5 @ 0xA @ 0b101)
  175. BR.S.L {v: rel} => le({v} @ 0`5 @ 4`5 @ 0xB @ 0b101)
  176. BR.S.GE {v: rel} => le({v} @ 0`5 @ 4`5 @ 0xC @ 0b101)
  177. BR.S.LE {v: rel} => le({v} @ 0`5 @ 4`5 @ 0xD @ 0b101)
  178. BR.S.G {v: rel} => le({v} @ 0`5 @ 4`5 @ 0xE @ 0b101)
  179. BRA {v: rel} => le({v} @ 0`5 @ 4`5 @ 0xF @ 0b101)
  180.  
  181. IN {d: reg}, [{s: reg} + {o: reg}] => le(0`10 @ {o} @ {s} @ {d} @ 0x0 @ 0b110)
  182. IN {d: reg}, [{s: reg} + {v: imm}] => le( {v} @ {s} @ {d} @ 0x1 @ 0b110)
  183. OUT [{d: reg} + {o: reg}], {s: reg} => le(0`10 @ {o} @ {s} @ {d} @ 0x2 @ 0b110)
  184. OUT [{d: reg} + {v: imm}], {s: reg} => le( {v} @ {s} @ {d} @ 0x3 @ 0b110)
  185.  
  186. SYS => le(0`10 @ 0`5 @ 0`5 @ 0`5 @ 0x0 @ 0b111)
  187. CLRK => le(0`10 @ 0`5 @ 0`5 @ 0`5 @ 0x1 @ 0b111)
  188. }
  189.  
  190. ; aliases
  191. #ruledef
  192. {
  193. MOV {d: reg}, {s: reg} => asm { OR {d}, {s}, zero }
  194. LD {d: reg}, {v: i32} => asm { OR {d}, v , zero }
  195.  
  196. CMP {l: reg}, {r: reg} => asm { SUB zero, {l}, {r}}
  197. CMP {l: reg}, {v: i32} => asm { SUB zero, {l}, v }
  198. CMP {v: i32}, {r: reg} => asm { SUB zero, v , {r}}
  199.  
  200. BIT {l: reg}, {r: reg} => asm { AND zero, {l}, {r}}
  201. BIT {l: reg}, {v: i32} => asm { AND zero, {l}, v }
  202. BIT {v: i32}, {r: reg} => asm { AND zero, v , {r}}
  203.  
  204. TEST {s: reg} => asm { OR zero, {s}, zero }
  205.  
  206. INC {d: reg} => asm { ADD {d}, {d}, 1 }
  207. INCC {d: reg} => asm { ADDC {d}, {d}, zero }
  208. DEC {d: reg} => asm { SUB {d}, {d}, 1 }
  209. DECB {d: reg} => asm { SUBB {d}, {d}, zero }
  210.  
  211. NEG {d: reg}, {s: reg} => asm { SUB {d}, zero, {s} }
  212. NEGB {d: reg}, {s: reg} => asm { SUBB {d}, zero, {s} }
  213.  
  214. NOT {d: reg}, {s: reg} => asm { XOR {d}, {s}, -1 }
  215.  
  216. LD {d: reg}, [{s: reg}] => asm { LD {d}, [{s} + zero] }
  217. LD {d: reg}, [{v: i32}] => asm { LD {d}, [zero + v] }
  218. ST [{d: reg}], {s: reg} => asm { ST [{d} + zero], {s} }
  219. ST [{v: i32}], {s: reg} => asm { ST [zero + v], {s} }
  220. LD8 {d: reg}, [{s: reg}] => asm { LD8 {d}, [{s} + zero] }
  221. LD8 {d: reg}, [{v: i32}] => asm { LD8 {d}, [zero + v] }
  222. ST8 [{d: reg}], {s: reg} => asm { ST8 [{d} + zero], {s} }
  223. ST8 [{v: i32}], {s: reg} => asm { ST8 [zero + v], {s} }
  224. LD16 {d: reg}, [{s: reg}] => asm { LD16 {d}, [{s} + zero] }
  225. LD16 {d: reg}, [{v: i32}] => asm { LD16 {d}, [zero + v] }
  226. ST16 [{d: reg}], {s: reg} => asm { ST16 [{d} + zero], {s} }
  227. ST16 [{v: i32}], {s: reg} => asm { ST16 [zero + v], {s} }
  228.  
  229. JP.EQ {s: reg} + {o: reg} => asm { JP.Z {s} + {o} }
  230. JP.NEQ {s: reg} + {o: reg} => asm { JP.NZ {s} + {o} }
  231. JP.U.L {s: reg} + {o: reg} => asm { JP.NC {s} + {o} }
  232. JP.U.GE {s: reg} + {o: reg} => asm { JP.C {s} + {o} }
  233.  
  234. JP.EQ [{s: reg} + {o: reg}] => asm { JP.Z [{s} + {o}] }
  235. JP.NEQ [{s: reg} + {o: reg}] => asm { JP.NZ [{s} + {o}] }
  236. JP.U.L [{s: reg} + {o: reg}] => asm { JP.NC [{s} + {o}] }
  237. JP.U.GE [{s: reg} + {o: reg}] => asm { JP.C [{s} + {o}] }
  238.  
  239. JP.EQ {s: reg} + {v: u32} => asm { JP.Z {s} + v }
  240. JP.NEQ {s: reg} + {v: u32} => asm { JP.NZ {s} + v }
  241. JP.U.L {s: reg} + {v: u32} => asm { JP.NC {s} + v }
  242. JP.U.GE {s: reg} + {v: u32} => asm { JP.C {s} + v }
  243.  
  244. JP.EQ [{s: reg} + {v: u32}] => asm { JP.Z [{s} + v] }
  245. JP.NEQ [{s: reg} + {v: u32}] => asm { JP.NZ [{s} + v] }
  246. JP.U.L [{s: reg} + {v: u32}] => asm { JP.NC [{s} + v] }
  247. JP.U.GE [{s: reg} + {v: u32}] => asm { JP.C [{s} + v] }
  248.  
  249. BR.EQ {v: u32} => asm { BR.Z v }
  250. BR.NEQ {v: u32} => asm { BR.NZ v }
  251. BR.U.L {v: u32} => asm { BR.NC v }
  252. BR.U.GE {v: u32} => asm { BR.C v }
  253.  
  254. JP.C {s: reg} => asm { JP.C {s} + zero }
  255. JP.Z {s: reg} => asm { JP.Z {s} + zero }
  256. JP.S {s: reg} => asm { JP.S {s} + zero }
  257. JP.O {s: reg} => asm { JP.O {s} + zero }
  258. JP.NC {s: reg} => asm { JP.NC {s} + zero }
  259. JP.NZ {s: reg} => asm { JP.NZ {s} + zero }
  260. JP.NS {s: reg} => asm { JP.NS {s} + zero }
  261. JP.NO {s: reg} => asm { JP.NO {s} + zero }
  262. JP.EQ {s: reg} => asm { JP.Z {s} + zero }
  263. JP.NEQ {s: reg} => asm { JP.NZ {s} + zero }
  264. JP.U.L {s: reg} => asm { JP.NC {s} + zero }
  265. JP.U.GE {s: reg} => asm { JP.C {s} + zero }
  266. JP.U.LE {s: reg} => asm { JP.U.LE {s} + zero }
  267. JP.U.G {s: reg} => asm { JP.U.G {s} + zero }
  268. JP.S.L {s: reg} => asm { JP.S.L {s} + zero }
  269. JP.S.GE {s: reg} => asm { JP.S.GE {s} + zero }
  270. JP.S.LE {s: reg} => asm { JP.S.LE {s} + zero }
  271. JP.S.G {s: reg} => asm { JP.S.G {s} + zero }
  272. JMP {s: reg} => asm { JMP {s} + zero }
  273.  
  274. JP.C [{s: reg}] => asm { JP.C [{s} + zero] }
  275. JP.Z [{s: reg}] => asm { JP.Z [{s} + zero] }
  276. JP.S [{s: reg}] => asm { JP.S [{s} + zero] }
  277. JP.O [{s: reg}] => asm { JP.O [{s} + zero] }
  278. JP.NC [{s: reg}] => asm { JP.NC [{s} + zero] }
  279. JP.NZ [{s: reg}] => asm { JP.NZ [{s} + zero] }
  280. JP.NS [{s: reg}] => asm { JP.NS [{s} + zero] }
  281. JP.NO [{s: reg}] => asm { JP.NO [{s} + zero] }
  282. JP.EQ [{s: reg}] => asm { JP.Z [{s} + zero] }
  283. JP.NEQ [{s: reg}] => asm { JP.NZ [{s} + zero] }
  284. JP.U.L [{s: reg}] => asm { JP.NC [{s} + zero] }
  285. JP.U.GE [{s: reg}] => asm { JP.C [{s} + zero] }
  286. JP.U.LE [{s: reg}] => asm { JP.U.LE [{s} + zero] }
  287. JP.U.G [{s: reg}] => asm { JP.U.G [{s} + zero] }
  288. JP.S.L [{s: reg}] => asm { JP.S.L [{s} + zero] }
  289. JP.S.GE [{s: reg}] => asm { JP.S.GE [{s} + zero] }
  290. JP.S.LE [{s: reg}] => asm { JP.S.LE [{s} + zero] }
  291. JP.S.G [{s: reg}] => asm { JP.S.G [{s} + zero] }
  292. JMP [{s: reg}] => asm { JMP [{s} + zero] }
  293.  
  294. JP.C {v: u32} => asm { JP.C zero + v }
  295. JP.Z {v: u32} => asm { JP.Z zero + v }
  296. JP.S {v: u32} => asm { JP.S zero + v }
  297. JP.O {v: u32} => asm { JP.O zero + v }
  298. JP.NC {v: u32} => asm { JP.NC zero + v }
  299. JP.NZ {v: u32} => asm { JP.NZ zero + v }
  300. JP.NS {v: u32} => asm { JP.NS zero + v }
  301. JP.NO {v: u32} => asm { JP.NO zero + v }
  302. JP.EQ {v: u32} => asm { JP.Z zero + v }
  303. JP.NEQ {v: u32} => asm { JP.NZ zero + v }
  304. JP.U.L {v: u32} => asm { JP.NC zero + v }
  305. JP.U.GE {v: u32} => asm { JP.C zero + v }
  306. JP.U.LE {v: u32} => asm { JP.U.LE zero + v }
  307. JP.U.G {v: u32} => asm { JP.U.G zero + v }
  308. JP.S.L {v: u32} => asm { JP.S.L zero + v }
  309. JP.S.GE {v: u32} => asm { JP.S.GE zero + v }
  310. JP.S.LE {v: u32} => asm { JP.S.LE zero + v }
  311. JP.S.G {v: u32} => asm { JP.S.G zero + v }
  312. JMP {v: u32} => asm { JMP zero + v }
  313.  
  314. JP.C [{v: u32}] => asm { JP.C [zero + v] }
  315. JP.Z [{v: u32}] => asm { JP.Z [zero + v] }
  316. JP.S [{v: u32}] => asm { JP.S [zero + v] }
  317. JP.O [{v: u32}] => asm { JP.O [zero + v] }
  318. JP.NC [{v: u32}] => asm { JP.NC [zero + v] }
  319. JP.NZ [{v: u32}] => asm { JP.NZ [zero + v] }
  320. JP.NS [{v: u32}] => asm { JP.NS [zero + v] }
  321. JP.NO [{v: u32}] => asm { JP.NO [zero + v] }
  322. JP.EQ [{v: u32}] => asm { JP.Z [zero + v] }
  323. JP.NEQ [{v: u32}] => asm { JP.NZ [zero + v] }
  324. JP.U.L [{v: u32}] => asm { JP.NC [zero + v] }
  325. JP.U.GE [{v: u32}] => asm { JP.C [zero + v] }
  326. JP.U.LE [{v: u32}] => asm { JP.U.LE [zero + v] }
  327. JP.U.G [{v: u32}] => asm { JP.U.G [zero + v] }
  328. JP.S.L [{v: u32}] => asm { JP.S.L [zero + v] }
  329. JP.S.GE [{v: u32}] => asm { JP.S.GE [zero + v] }
  330. JP.S.LE [{v: u32}] => asm { JP.S.LE [zero + v] }
  331. JP.S.G [{v: u32}] => asm { JP.S.G [zero + v] }
  332. JMP [{v: u32}] => asm { JMP [zero + v] }
  333.  
  334. IN {d: reg}, [{s: reg}] => asm { IN {d}, [{s} + zero] }
  335. IN {d: reg}, [{v: i32}] => asm { IN {d}, [zero + v] }
  336. OUT [{d: reg}], {s: reg} => asm { OUT [{d} + zero], {s} }
  337. OUT [{v: i32}], {s: reg} => asm { OUT [zero + v], {s} }
  338. }
  339.  
  340. ; macros
  341. #ruledef
  342. {
  343. PUSH {s: reg} => asm {
  344. ST [sp], {s}
  345. SUB sp, sp, 4
  346. }
  347.  
  348. POP {d: reg} => asm {
  349. ADD sp, sp, 4
  350. LD {d}, [sp]
  351. }
  352.  
  353. PUSH8 {s: reg} => asm {
  354. ST8 [sp], {s}
  355. SUB sp, sp, 4
  356. }
  357.  
  358. POP8 {d: reg} => asm {
  359. ADD sp, sp, 4
  360. LD8 {d}, [sp]
  361. }
  362.  
  363. PUSH16 {s: reg} => asm {
  364. ST16 [sp], {s}
  365. SUB sp, sp, 4
  366. }
  367.  
  368. POP16 {d: reg} => asm {
  369. ADD sp, sp, 4
  370. LD16 {d}, [sp]
  371. }
  372.  
  373. CALL {s: reg} => {
  374. addr = $ + 12
  375. assert(addr < 8192)
  376.  
  377. asm {
  378. MOV bp, sp
  379. LD ra, addr`14
  380. JMP {s}
  381. }
  382. }
  383. CALL {s: reg} => {
  384. addr = $ + 12
  385. assert(addr >= 8192)
  386.  
  387. asm {
  388. MOV bp, sp
  389. LD ra, (addr + 4)
  390. JMP {s}
  391. }
  392. }
  393.  
  394. CALL [{s: reg}] => {
  395. addr = $ + 12
  396. assert(addr < 8192)
  397.  
  398. asm {
  399. MOV bp, sp
  400. LD ra, addr`14
  401. JMP [{s}]
  402. }
  403. }
  404. CALL [{s: reg}] => {
  405. addr = $ + 12
  406. assert(addr >= 8192)
  407.  
  408. asm {
  409. MOV bp, sp
  410. LD ra, (addr + 4)
  411. JMP [{s}]
  412. }
  413. }
  414.  
  415. CALL {v: u32} => {
  416. assert(v < 8192)
  417. addr = $ + 12
  418. assert(addr < 8192)
  419.  
  420. asm {
  421. MOV bp, sp
  422. LD ra, addr`14
  423. JMP v`14
  424. }
  425. }
  426. CALL {v: u32} => {
  427. assert(v < 8192)
  428. addr = $ + 12
  429. assert(addr >= 8192)
  430.  
  431. asm {
  432. MOV bp, sp
  433. LD ra, (addr + 4)
  434. JMP v`14
  435. }
  436. }
  437. CALL {v: u32} => {
  438. assert(v >= 8192)
  439. addr = $ + 16
  440. assert(addr < 8192)
  441.  
  442. asm {
  443. MOV bp, sp
  444. LD ra, addr`14
  445. JMP v
  446. }
  447. }
  448. CALL {v: u32} => {
  449. assert(v >= 8192)
  450. addr = $ + 16
  451. assert(addr >= 8192)
  452.  
  453. asm {
  454. MOV bp, sp
  455. LD ra, (addr + 4)
  456. JMP v
  457. }
  458. }
  459.  
  460. CALL [{v: u32}] => {
  461. assert(v < 8192)
  462. addr = $ + 12
  463. assert(addr < 8192)
  464.  
  465. asm {
  466. MOV bp, sp
  467. LD ra, addr`14
  468. JMP [v`14]
  469. }
  470. }
  471. CALL [{v: u32}] => {
  472. assert(v < 8192)
  473. addr = $ + 12
  474. assert(addr >= 8192)
  475.  
  476. asm {
  477. MOV bp, sp
  478. LD ra, (addr + 4)
  479. JMP [v`14]
  480. }
  481. }
  482. CALL [{v: u32}] => {
  483. assert(v >= 8192)
  484. addr = $ + 16
  485. assert(addr < 8192)
  486.  
  487. asm {
  488. MOV bp, sp
  489. LD ra, addr`14
  490. JMP [v]
  491. }
  492. }
  493. CALL [{v: u32}] => {
  494. assert(v >= 8192)
  495. addr = $ + 16
  496. assert(addr >= 8192)
  497.  
  498. asm {
  499. MOV bp, sp
  500. LD ra, (addr + 4)
  501. JMP [v]
  502. }
  503. }
  504.  
  505. RET {v: u12} => asm {
  506. ADD sp, bp, (v`14 << 2)`14
  507. JMP ra
  508. }
  509.  
  510. CALLS => {
  511. addr = $ + 8
  512. assert(addr < 8192)
  513.  
  514. asm {
  515. LD ra, addr`14
  516. SYS
  517. }
  518. }
  519. CALLS => {
  520. addr = $ + 8
  521. assert(addr >= 8192)
  522.  
  523. asm {
  524. LD ra, (addr + 4)
  525. SYS
  526. }
  527. }
  528.  
  529. RETS => asm {
  530. CLRK
  531. JMP ra
  532. }
  533. }
  534.  
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