library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.std_logic_unsigned.all;

entity serialrx is
  generic (
    CLOCKRATE : integer := 100000000;
    BAUDRATE  : integer := 115200);
  port (
    clk : in std_logic;
    rst : in std_logic;
    dout : out std_logic_vector(7 downto 0);
    rxdone : out std_logic;
    RX : in std_logic
  );

end serialrx;

architecture Behavioral of serialrx is

  constant TBIT : integer := CLOCKRATE / BAUDRATE;

  type states is (IDLE, START, DATA, STOP);
  signal state, state_next : states;

  signal rx_start, rx_negedge : std_logic;
  signal rdata, rdata_reg : std_logic_vector(7 downto 0);
  signal rbits, rbits_reg : integer range 0 to 8;
  signal rxdone_reg : std_logic;
  signal timecnt, tmax : integer range 0 to TBIT;
  signal rxd : std_logic_vector(2 downto 0);


begin

  process (clk) begin
    if rising_edge(clk) then
      rxd <= rxd(1 downto 0) & RX;
    end if;
  end process;

  rx_negedge <= '1' when rxd(2 downto 1) = "10" else '0';
  rx_start <= '1' when (rx_negedge = '1' AND (state = IDLE)) else '0';

  process (clk) begin
    if rising_edge(clk) then
      if rst then
        timecnt <= 0;
      elsif timecnt < tmax then
        timecnt <= timecnt + 1;
      else
        timecnt <= 0;
      end if;
    end if;
  end process;

  process (clk) begin
    if rising_edge(clk) then
      if rst then
        state <= IDLE;
      else
        state <= state_next;
      end if;
    end if;
  end process;

  process (clk) begin
    if rising_edge(clk) then
      if rst then
        rdata_reg <= (others => '0');
        rbits_reg <= 0;
        rxdone_reg <= '0';
      else
        rdata_reg <= rdata;
        rbits_reg <= rbits;
        rxdone_reg <= rxdone;
      end if;
    end if;
  end process;

  process (all) begin
    rdata <= rdata_reg;
    rbits <= rbits_reg;
    rxdone <= rxdone_reg;
    case(state) is
    when IDLE =>
      rxdone <= '0';
      tmax <= 0;
      rbits <= 0;
      if rx_start then
        state_next <= START;
      else
        state_next <= IDLE;
      end if;
    when START =>
      rdata <= (others => '0');
      rbits <= 0;
      tmax <= TBIT/2 - 1;
      if timecnt = tmax then
        state_next <= DATA;
      else
        state_next <= START;
      end if;
    when DATA =>
      tmax <= TBIT - 1;
      state_next <= DATA;
      if timecnt = tmax then
        rdata <= rxd(2) & rdata(7 downto 1);
        if rbits = 7 then
          state_next <= STOP;
        else
          rbits <= rbits_reg + 1;
        end if;
      end if;
    when STOP =>
      tmax <= TBIT - 1;
      rbits <= 0;
      if timecnt = tmax then
        rxdone <= '1';
        state_next <= IDLE;
      else
        state_next <= STOP;
      end if;
    when others =>
      state_next <= IDLE;
      rxdone <= '0';
      rdata <= (others => '0');
      rbits <= 0;
    end case;
  end process;

  dout <= rdata_reg;

end Behavioral;