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Matqux

I2S_testbench

Feb 27th, 2024
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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 02/25/2024 06:55:40 PM
  7. // Design Name:
  8. // Module Name: Testbench
  9. // Project Name:
  10. // Target Devices:
  11. // Tool Versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21.  
  22.  
  23.  
  24. module Testbench;
  25.  
  26. reg clk_system;
  27. reg clk_I2S;
  28.  
  29. initial
  30. begin
  31.     clk_system = 1'b0;
  32.     clk_I2S = 1'b0;
  33. end
  34.  
  35. always
  36. begin
  37.     clk_system = ~clk_system;
  38.     #1; //ns -> f = 1MHz
  39. end
  40.  
  41. always
  42. begin
  43.     clk_I2S = ~clk_I2S;
  44.     #10_416.667; //ns -> f = 96kHz
  45. end
  46.  
  47. reg rstn;
  48. initial
  49. begin
  50.     rstn = 1'b0;
  51.     #50_000;
  52.     rstn = 1'b1;
  53. end
  54.  
  55. reg en;
  56. initial
  57. begin
  58.     en = 1'b1;
  59.     #3_000_000;
  60.     en = 1'b0;
  61. end
  62.  
  63. wire lrclk;
  64. wire bclk;
  65. wire sd;
  66.  
  67. wire [23:0] adc_data;
  68. wire adc_valid_l;
  69. wire adc_valid_r;
  70.  
  71. I2S_receiver receiver
  72. (
  73.     .clk(clk_system),
  74.     .rstn(rstn),
  75.     .en(en),
  76.     .lrclk(lrclk),
  77.     .bclk(bclk),
  78.     .sdi(sd),
  79.  
  80.     .adc_data(adc_data),
  81.     .adc_valid_l(adc_valid_l),
  82.     .adc_valid_r(adc_valid_r)
  83. );
  84.  
  85. I2S_transmitter transmitter
  86. (
  87.     .clk(clk_I2S),
  88.     .rstn(rstn),
  89.     .lrclk(lrclk),
  90.     .bclk(bclk),
  91.     .sdo(sd)
  92. );
  93.  
  94. endmodule
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