Labb3 överkurs 2

LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY control IS
    PORT ( Start, Clock: IN std_logic;
    Ready: OUT std_logic;
    Lamp: OUT std_logic);
END ENTITY control;

ARCHITECTURE counter OF control IS

    SUBTYPE tillstand IS integer RANGE 0 TO 19;
    SIGNAL nuvarande: tillstand;
    BEGIN
        Raknare: PROCESS(clock, nuvarande, start)
            BEGIN

            IF rising_edge(clock) THEN
                Ready <= '0';
                IF (nuvarande = 0 AND start = '1') THEN
                    nuvarande <= 1;
                ELSIF nuvarande = 19 THEN
                    nuvarande <= 0;
                    Ready <= '1';
                ELSIF nuvarande > 0 THEN
                    nuvarande <= nuvarande + 1;
                END IF;
            END IF;
        END PROCESS;



    Lampa: PROCESS(nuvarande)
        BEGIN
            Lamp <= '0';
            IF nuvarande = 0 THEN
                Lamp <= '0';
            ELSIF nuvarande > 0 THEN
                Lamp <= '1';
            END IF;
    END PROCESS;
END ARCHITECTURE counter;