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  1. //
  2. // Amstrad CPC 40010 Gate Array implementation in Verilog.
  3. //
  4. // Ash Evans. 2016
  5. //
  6. //
  7. // Translated from the superb PDF schematic by Gerald, which he dechipered from a decapped 40010 chip...
  8. //
  9. // http://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg133284/#msg133284
  10. //
  11.  
  12.  
  13. // PDF page 1...
  14. module ga_400010 (
  15.     input PAD_RESET_N,
  16.     input PAD_MREQ_N,
  17.     input PAD_M1_N,
  18.     input PAD_RD_N,
  19.     input PAD_IORQ_N,
  20.     input PAD_16MHZ,
  21.     input PAD_HSYNC,
  22.     input PAD_VSYNC,
  23.     input PAD_DISPEN,
  24.     input PAD_A15,
  25.     input PAD_A14,
  26.     input [7:0] PAD_D,
  27.    
  28.     output PAD_RAS_N,
  29.     output PAD_READY,
  30.     output PAD_CASAD_N,
  31.     output PAD_CPU_N,       // Should be _N on PDF page 1 as well?
  32.     output PAD_MWE_N,
  33.     output PAD_244E_N,
  34.     output PAD_CCLK,
  35.     output PAD_PHI_N,
  36.    
  37.     output PAD_CAS_N,
  38.    
  39.     output PAD_SYNC_N,
  40.     output PAD_INT_N,
  41.    
  42.     output PAD_RED,
  43.     output PAD_GREEN,
  44.     output PAD_BLUE,
  45.    
  46.     output PAD_ROMEN_N,
  47.     output PAD_RAMRD_N
  48. );
  49.  
  50.  
  51. wire U121 = !PAD_RESET_N;
  52. wire CLK_16M_N = !PAD_16MHZ;    // U120.
  53.  
  54. wire S0, S1, S2, S3, S4, S5, S6, S7;
  55. sequencer sequencer_inst
  56. (
  57.     .RESET(U121) ,  // input  RESET
  58.     .M1_N(PAD_M1_N) ,   // input  M1_N
  59.     .IORQ_N(PAD_IORQ_N) ,   // input  IORQ_N
  60.     .RD_N(PAD_RD_N) ,   // input  RD_N
  61.     .CLK_16M_N(CLK_16M_N) , // input  CLK_16M_N
  62.     .S0(S0) ,   // output  S0
  63.     .S1(S1) ,   // output  S1
  64.     .S2(S2) ,   // output  S2
  65.     .S3(S3) ,   // output  S3
  66.     .S4(S4) ,   // output  S4
  67.     .S5(S5) ,   // output  S5
  68.     .S6(S6) ,   // output  S6
  69.     .S7(S7)     // output  S7
  70. );
  71.  
  72. sequence_decoder sequence_decoder_inst
  73. (
  74.     .CLK_16M_N(CLK_16M_N) , // input  CLK_16M_N
  75.     .S0(S0) ,   // input  S0
  76.     .S1(S1) ,   // input  S1
  77.     .S2(S2) ,   // input  S2
  78.     .S3(S3) ,   // input  S3
  79.     .S4(S4) ,   // input  S4
  80.     .S5(S5) ,   // input  S5
  81.     .S6(S6) ,   // input  S6
  82.     .S7(S7) ,   // input  S7
  83.     .RD_N(PAD_RD_N) ,   // input  RD_N
  84.     .IORQ_N(PAD_IORQ_N) ,   // input  IORQ_N
  85.     .PHI_N(PAD_PHI_N) , // output  PHI_N
  86.     .RAS_N(PAD_RAS_N) , // output  RAS_N
  87.     .READY(PAD_READY) , // output  READY
  88.     .CASAD_N(PAD_CASAD_N) , // output  CASAD_N
  89.     .CPU_N(PAD_CPU_N) , // output  CPU_N
  90.     .CCLK(PAD_CCLK) ,   // output  CCLK
  91.     .MWE_N(PAD_MWE_N) , // output  MWE_N
  92.     .E244_N(PAD_244E_N)     // output  E244_N. NOTE: Had to put the "E" at the start on the signal name (on the module).
  93. );
  94.  
  95. cas_generation cas_generation_inst
  96. (
  97.     .RESET(U121) ,  // input  RESET
  98.     .M1_N(PAD_M1_N) ,   // input  M1_N
  99.     .PHI_N(PAD_PHI_N) , // input  PHI_N
  100.     .MREQ_N(PAD_MREQ_N) ,   // input  MREQ_N
  101.     .S0(S0) ,   // input  S0
  102.     .S1(S1) ,   // input  S1
  103.     .S2(S2) ,   // input  S2
  104.     .S3(S3) ,   // input  S3
  105.     .S4(S4) ,   // input  S4
  106.     .S5(S5) ,   // input  S5
  107.     .S6(S6) ,   // input  S6
  108.     .S7(S7) ,   // input  S7
  109.     .CLK_16M_N(CLK_16M_N) , // input  CLK_16M_N
  110.     .CAS_N(PAD_CAS_N)   // output  CAS_N
  111. );
  112.  
  113.  
  114. wire [4:2] HCNT;
  115. wire IRQ_RESET;
  116. wire MODE_SYNC;
  117. sync_gen sync_gen_inst
  118. (
  119.     .HSYNC(PAD_HSYNC) , // input  HSYNC
  120.     .CCLK(PAD_CCLK) ,       // input  CCLK
  121.     .RESET(U121) ,          // input  RESET
  122.     .VSYNC(PAD_VSYNC) , // input  VSYNC
  123.     .IORQ_N(PAD_IORQ_N) ,   // input  IORQ_N
  124.     .M1_N(PAD_M1_N) ,           // input  M1_N
  125.     .IRQ_RESET(IRQ_RESET) , // input  IRQ_RESET
  126.     .NSYNC(PAD_SYNC_N) ,        // output  NSYNC
  127.     .MODE_SYNC(MODE_SYNC) , // output  MODE_SYNC
  128.     .HCNT(HCNT) ,               // output [4:2] HCNT
  129.     .INT_N(PAD_INT_N)       // output  INT_N
  130. );
  131.  
  132. wire [15:0] INKR4;
  133. wire [15:0] INKR3;
  134. wire [15:0] INKR2;
  135. wire [15:0] INKR1;
  136. wire [15:0] INKR0;
  137. wire [1:0] MODE;
  138. wire [4:0] BORDER;
  139. wire HROMEN;
  140. wire LROMEN;
  141. registers registers_inst
  142. (
  143.     .RESET(U121) ,  // input  RESET
  144.     .M1_N(PAD_M1_N) ,   // input  M1_N
  145.     .A14(PAD_A14) ,     // input  A14
  146.     .A15(PAD_A15) ,     // input  A15
  147.     .IORQ_N(PAD_IORQ_N) ,   // input  IORQ_N
  148.     .S0(S0) ,   // input  S0
  149.     .S7(S7) ,   // input  S7
  150.     .D(PAD_D) ,     // input [7:0] D
  151.     .BORDER(BORDER) ,   // output [4:0] BORDER
  152.     .IRQ_RESET(IRQ_RESET) , // output  IRQ_RESET
  153.     .HROMEN(HROMEN) ,   // output  HROMEN
  154.     .LROMEN(LROMEN) ,   // output  LROMEN
  155.     .MODE(MODE) ,       // output [1:0] MODE
  156.     .INKR4(INKR4) , // output [15:0] INKR4
  157.     .INKR3(INKR3) , // output [15:0] INKR3
  158.     .INKR2(INKR2) , // output [15:0] INKR2
  159.     .INKR1(INKR1) , // output [15:0] INKR1
  160.     .INKR0(INKR0)       // output [15:0] INKR0
  161. );
  162.  
  163.  
  164. rom_ram_mapping rom_ram_mapping_inst
  165. (
  166.     .LROMEN(LROMEN) ,   // input  LROMEN
  167.     .A15(PAD_A15) , // input  A15
  168.     .A14(PAD_A14) , // input  A14
  169.     .HROMEN(HROMEN) ,   // input  HROMEN
  170.     .MREQ_N(PAD_MREQ_N) ,   // input  MREQ_N
  171.     .RD_N(PAD_RD_N) ,   // input  RD_N
  172.     .ROMEN_N(PAD_ROMEN_N) , // output  ROMEN_N
  173.     .RAMRD_N(PAD_RAMRD_N)   // output  RAMRD_N
  174. );
  175.  
  176. wire DISPEN_BUF;
  177. wire [7:0] VIDEO_BUF;
  178. video_buffer video_buffer_inst
  179. (
  180.     .DISPEN(PAD_DISPEN) ,   // input  DISPEN
  181.     .S3(S3) ,   // input  S3
  182.     .CAS_N_IN(PAD_CAS_N) ,  // input  CAS_N_IN
  183.     .D(PAD_D) , // input [7:0] D
  184.     .DISPEN_BUF(DISPEN_BUF) ,   // output  DISPEN_BUF
  185.     .VIDEO_BUF(VIDEO_BUF)   // output [7:0] VIDEO_BUF
  186. );
  187.  
  188. wire LOAD;
  189. wire COLOUR_KEEP;
  190. wire INK_SEL;
  191. wire BORDER_SEL;
  192. wire SHIFT;
  193. wire KEEP;
  194. wire MODE_IS_2;
  195. wire MODE_IS_0;
  196. wire BLUE_OE_N;
  197. wire BLUE;
  198. wire GREEN_OE_N;
  199. wire GREEN;
  200. wire RED_OE_N;
  201. wire RED;
  202. video_control video_control_inst
  203. (
  204.     .CLK_16M_N(CLK_16M_N) , // input  CLK_16M_N
  205.     .DISPEN_BUF(DISPEN_BUF) ,   // input  DISPEN_BUF
  206.     .S5(S5) ,   // input  S5
  207.     .S6(S6) ,   // input  S6
  208.     .PHI_N(PAD_PHI_N) , // input  PHI_N
  209.     .MODE(MODE) ,   // input [1:0] MODE
  210.     .MODE_SYNC(MODE_SYNC) , // input  MODE_SYNC
  211.     .LOAD(LOAD) ,   // output  LOAD
  212.     .COLOUR_KEEP(COLOUR_KEEP) , // output  COLOUR_KEEP
  213.     .INK_SEL(INK_SEL) , // output  INK_SEL
  214.     .BORDER_SEL(BORDER_SEL) ,   // output  BORDER_SEL
  215.     .SHIFT(SHIFT) , // output  SHIFT
  216.     .KEEP(KEEP) ,   // output  KEEP
  217.     .MODE_IS_2(MODE_IS_2) , // output  MODE_IS_2
  218.     .MODE_IS_0(MODE_IS_0)   // output  MODE_IS_0
  219. );
  220.  
  221. wire [3:0] CIDX;
  222. video_shift video_shift_inst
  223. (
  224.     .VIDEO(VIDEO_BUF) , // input [7:0] VIDEO
  225.     .KEEP(KEEP) ,   // input  KEEP
  226.     .LOAD(LOAD) ,   // input  LOAD
  227.     .SHIFT(SHIFT) , // input  SHIFT
  228.     .CLK_16M_N(CLK_16M_N) , // input  CLK_16M_N
  229.     .CIDX(CIDX)     // output [3:0] CIDX
  230. );
  231.  
  232. wire [4:0] COLOUR;
  233. colour_mux_full colour_mux_full_inst
  234. (
  235.     .BORDER(BORDER) ,   // input [4:0] BORDER
  236.     .INKR4(INKR4) , // input [15:0] INKR4
  237.     .INKR3(INKR3) , // input [15:0] INKR3
  238.     .INKR2(INKR2) , // input [15:0] INKR2
  239.     .INKR1(INKR1) , // input [15:0] INKR1
  240.     .INKR0(INKR0) , // input [15:0] INKR0
  241.     .COLOUR_KEEP(COLOUR_KEEP) , // input  COLOUR_KEEP
  242.     .INK_SEL(INK_SEL) , // input  INK_SEL
  243.     .BORDER_SEL(BORDER_SEL) ,   // input  BORDER_SEL
  244.     .MODE_IS_0(MODE_IS_0) , // input  MODE_IS_0
  245.     .MODE_IS_2(MODE_IS_2) , // input  MODE_IS_2
  246.     .CIDX(CIDX) ,   // input [3:0] CIDX
  247.     .CLK_16M_N(CLK_16M_N) , // input  CLK_16M_N
  248.     .COLOUR(COLOUR)     // output [4:0] COLOUR
  249. );
  250.  
  251.  
  252. colour_decode colour_decode_inst
  253. (
  254.     .HCNT(HCNT) ,   // input [4:2] HCNT
  255.     .HSYNC(PAD_HSYNC) , // input  HSYNC
  256.     .COLOUR(COLOUR) ,   // input [4:0] COLOUR
  257.     .CLK_16M_N(CLK_16M_N) , // input  CLK_16M_N
  258.     .BLUE_OE_N(BLUE_OE_N) , // output  BLUE_OE_N
  259.     .BLUE(BLUE) ,   // output  BLUE
  260.     .GREEN_OE_N(GREEN_OE_N) ,   // output  GREEN_OE_N
  261.     .GREEN(GREEN) , // output  GREEN
  262.     .RED_OE_N(RED_OE_N) ,   // output  RED_OE_N
  263.     .RED(RED)   // output  RED
  264. );
  265.  
  266. assign PAD_RED = (!RED_OE_N) ? RED : 1'bz;
  267. assign PAD_GREEN = (!GREEN_OE_N) ? GREEN : 1'bz;
  268. assign PAD_BLUE = (!BLUE_OE_N) ? BLUE : 1'bz;
  269.  
  270. endmodule
  271.  
  272.  
  273.  
  274. // PDF page 2...
  275. module sequencer (
  276.     input RESET,
  277.     input M1_N,
  278.     input IORQ_N,
  279.     input RD_N,
  280.    
  281.     input CLK_16M_N,
  282.    
  283.     output S0,
  284.     output S1,
  285.     output S2,
  286.     output S3,
  287.     output S4,
  288.     output S5,
  289.     output S6,
  290.     output S7
  291. );
  292.  
  293. wire U202 = RESET & !M1_N & !IORQ_N & !RD_N;
  294.  
  295. wire U215 = U216_REG & !U217_REG;
  296.  
  297. wire U204 = U202 | U215;
  298.  
  299. reg U201_REG;
  300. reg U205_REG;
  301. reg U207_REG;
  302. reg U209_REG;
  303. reg U211_REG;
  304. reg U213_REG;
  305. reg U216_REG;
  306. reg U217_REG;
  307.  
  308. always @(posedge CLK_16M_N) U201_REG <= !U217_REG;
  309. always @(posedge CLK_16M_N) U205_REG <= U204 | U201_REG;    // U203 is the OR gate.
  310. always @(posedge CLK_16M_N) U207_REG <= U204 | U205_REG;    // U206 is the OR gate.
  311. always @(posedge CLK_16M_N) U209_REG <= U204 | U207_REG;    // U208 is the OR gate.
  312. always @(posedge CLK_16M_N) U211_REG <= U204 | U209_REG;    // U210 is the OR gate.
  313. always @(posedge CLK_16M_N) U213_REG <= U204 | U211_REG;    // U212 is the OR gate.
  314. always @(posedge CLK_16M_N) U216_REG <= U204 | U213_REG;    // U214 is the OR gate.
  315. always @(posedge CLK_16M_N) U217_REG <= U216_REG;
  316.  
  317. assign S0 = U201_REG;
  318. assign S1 = U205_REG;
  319. assign S2 = U207_REG;
  320. assign S3 = U209_REG;
  321. assign S4 = U211_REG;
  322. assign S5 = U213_REG;
  323. assign S6 = U216_REG;
  324. assign S7 = U217_REG;
  325.  
  326. endmodule
  327.  
  328.  
  329.  
  330. // PDF page 3...
  331. module sequence_decoder (
  332.     input CLK_16M_N,
  333.    
  334.     input S0,
  335.     input S1,
  336.     input S2,
  337.     input S3,
  338.     input S4,
  339.     input S5,
  340.     input S6,
  341.     input S7,
  342.        
  343.     input RD_N,
  344.     input IORQ_N,
  345.  
  346.     output reg PHI_N,
  347.     output reg RAS_N,
  348.     output READY,
  349.     output CASAD_N,
  350.     output CPU_N,
  351.     output CCLK,
  352.     output MWE_N,
  353.     output E244_N
  354. );
  355.  
  356.  
  357. always @(posedge CLK_16M_N) PHI_N <= (S1 ^ S3) | (S5 ^ S7);
  358.  
  359. always @(posedge CLK_16M_N) RAS_N <= (S6 | !S2) & S0;
  360.  
  361.  
  362. reg CASAD_REG;
  363. always @(posedge CLK_16M_N) CASAD_REG <= !RAS_N;
  364. assign CASAD_N = !CASAD_REG;
  365.  
  366.  
  367. wire U314 = READY & CASAD_REG;
  368. wire U304 = ! (S3 & !S6);
  369.  
  370. assign READY = U314 & U304;
  371.  
  372. assign CPU_N = ! (S1 & !S7);
  373.  
  374. assign CCLK = S2 | S5;
  375.  
  376. assign MWE_N = ! (S0 & S5 & RD_N);
  377.  
  378. assign E244_N = ! (S2 & S3 & !IORQ_N);
  379.  
  380. endmodule
  381.  
  382.  
  383.  
  384. // PDF pages 4 and 5...
  385. module registers(
  386.     input RESET,
  387.     input M1_N,
  388.     input A14,
  389.     input A15,
  390.     input IORQ_N,
  391.     input S0,
  392.     input S7,
  393.    
  394.     input [7:0] D,
  395.    
  396.     output reg [4:0] BORDER,
  397.     output IRQ_RESET,
  398.     output reg HROMEN,
  399.     output reg LROMEN,
  400.     output reg [1:0] MODE,
  401.    
  402.     output reg [15:0] INKR4,
  403.     output reg [15:0] INKR3,
  404.     output reg [15:0] INKR2,
  405.     output reg [15:0] INKR1,
  406.     output reg [15:0] INKR0
  407.    
  408.     /*
  409.     // Extra 32 colours...
  410.     output reg [31:0] INKR4,
  411.     output reg [31:0] INKR3,
  412.     output reg [31:0] INKR2,
  413.     output reg [31:0] INKR1,
  414.     output reg [31:0] INKR0
  415.     */
  416. );
  417.  
  418.  
  419. wire U401 = M1_N & A14 & !A15 & !IORQ_N & S0 & S7;
  420.  
  421. wire U402 = U401 & !D[7] & !D[6];
  422.  
  423. wire U408 = U401 & !D[7] & D[6] & INKSEL[4];
  424.  
  425. wire U414 = U401 & D[7] & !D[6];
  426.  
  427. reg [4:0] INKSEL;
  428. always @(posedge U402) INKSEL <= D[4:0];
  429.  
  430. always @(posedge U408) BORDER <= D[4:0];
  431.  
  432.  
  433. assign IRQ_RESET = U414 & D[4];
  434.  
  435. always @(posedge U414) HROMEN <= D[3];
  436. always @(posedge U414) LROMEN <= D[2];
  437. always @(posedge U414) MODE[1] <= D[1];
  438. always @(posedge U414) MODE[0] <= D[0];
  439.  
  440.  
  441. wire U420 = U401 & !D[7] & D[6];
  442.  
  443. wire INKR_0_E  = U420 & INKSEL == 5'b00000;
  444. wire INKR_1_E  = U420 & INKSEL == 5'b00001;
  445. wire INKR_2_E  = U420 & INKSEL == 5'b00010;
  446. wire INKR_3_E  = U420 & INKSEL == 5'b00011;
  447. wire INKR_4_E  = U420 & INKSEL == 5'b00100;
  448. wire INKR_5_E  = U420 & INKSEL == 5'b00101;
  449. wire INKR_6_E  = U420 & INKSEL == 5'b00110;
  450. wire INKR_7_E  = U420 & INKSEL == 5'b00111;
  451. wire INKR_8_E  = U420 & INKSEL == 5'b01000;
  452. wire INKR_9_E  = U420 & INKSEL == 5'b01001;
  453. wire INKR_10_E = U420 & INKSEL == 5'b01010;
  454. wire INKR_11_E = U420 & INKSEL == 5'b01011;
  455. wire INKR_12_E = U420 & INKSEL == 5'b01100;
  456. wire INKR_13_E = U420 & INKSEL == 5'b01101;
  457. wire INKR_14_E = U420 & INKSEL == 5'b01110;
  458. wire INKR_15_E = U420 & INKSEL == 5'b01111;
  459.  
  460. always @(posedge INKR_0_E)  {INKR4[0],  INKR3[0],  INKR2[0],  INKR1[0],  INKR0[0]} <= D[4:0];
  461. always @(posedge INKR_1_E)  {INKR4[1],  INKR3[1],  INKR2[1],  INKR1[1],  INKR0[1]} <= D[4:0];
  462. always @(posedge INKR_2_E)  {INKR4[2],  INKR3[2],  INKR2[2],  INKR1[2],  INKR0[2]} <= D[4:0];
  463. always @(posedge INKR_3_E)  {INKR4[3],  INKR3[3],  INKR2[3],  INKR1[3],  INKR0[3]} <= D[4:0];
  464. always @(posedge INKR_4_E)  {INKR4[4],  INKR3[4],  INKR2[4],  INKR1[4],  INKR0[4]} <= D[4:0];
  465. always @(posedge INKR_5_E)  {INKR4[5],  INKR3[5],  INKR2[5],  INKR1[5],  INKR0[5]} <= D[4:0];
  466. always @(posedge INKR_6_E)  {INKR4[6],  INKR3[6],  INKR2[6],  INKR1[6],  INKR0[6]} <= D[4:0];
  467. always @(posedge INKR_7_E)  {INKR4[7],  INKR3[7],  INKR2[7],  INKR1[7],  INKR0[7]} <= D[4:0];
  468. always @(posedge INKR_8_E)  {INKR4[8],  INKR3[8],  INKR2[8],  INKR1[8],  INKR0[8]} <= D[4:0];
  469. always @(posedge INKR_9_E)  {INKR4[9],  INKR3[9],  INKR2[9],  INKR1[9],  INKR0[9]} <= D[4:0];
  470. always @(posedge INKR_10_E) {INKR4[10], INKR3[10], INKR2[10], INKR1[10], INKR0[10]} <= D[4:0];
  471. always @(posedge INKR_11_E) {INKR4[11], INKR3[11], INKR2[11], INKR1[11], INKR0[11]} <= D[4:0];
  472. always @(posedge INKR_12_E) {INKR4[12], INKR3[12], INKR2[12], INKR1[12], INKR0[12]} <= D[4:0];
  473. always @(posedge INKR_13_E) {INKR4[13], INKR3[13], INKR2[13], INKR1[13], INKR0[13]} <= D[4:0];
  474. always @(posedge INKR_14_E) {INKR4[14], INKR3[14], INKR2[14], INKR1[14], INKR0[14]} <= D[4:0];
  475. always @(posedge INKR_15_E) {INKR4[15], INKR3[15], INKR2[15], INKR1[15], INKR0[15]} <= D[4:0];
  476.  
  477.  
  478. // Extra 32 colours!...
  479. /*
  480. wire INKR_16_E = U420 & INKSEL == 5'b10000;
  481. wire INKR_17_E = U420 & INKSEL == 5'b10001;
  482. wire INKR_18_E = U420 & INKSEL == 5'b10010;
  483. wire INKR_19_E = U420 & INKSEL == 5'b10011;
  484. wire INKR_20_E = U420 & INKSEL == 5'b10100;
  485. wire INKR_21_E = U420 & INKSEL == 5'b10101;
  486. wire INKR_22_E = U420 & INKSEL == 5'b10110;
  487. wire INKR_23_E = U420 & INKSEL == 5'b10111;
  488. wire INKR_24_E = U420 & INKSEL == 5'b11000;
  489. wire INKR_25_E = U420 & INKSEL == 5'b11001;
  490. wire INKR_26_E = U420 & INKSEL == 5'b11010;
  491. wire INKR_27_E = U420 & INKSEL == 5'b11011;
  492. wire INKR_28_E = U420 & INKSEL == 5'b11100;
  493. wire INKR_29_E = U420 & INKSEL == 5'b11101;
  494. wire INKR_30_E = U420 & INKSEL == 5'b11110;
  495. wire INKR_31_E = U420 & INKSEL == 5'b11111;
  496.  
  497. always @(posedge INKR_16_E) {INKR4[16], INKR3[16], INKR2[16], INKR1[16], INKR0[16]} <= D[4:0];
  498. always @(posedge INKR_17_E) {INKR4[17], INKR3[17], INKR2[17], INKR1[17], INKR0[17]} <= D[4:0];
  499. always @(posedge INKR_18_E) {INKR4[18], INKR3[18], INKR2[18], INKR1[18], INKR0[18]} <= D[4:0];
  500. always @(posedge INKR_19_E) {INKR4[19], INKR3[19], INKR2[19], INKR1[19], INKR0[19]} <= D[4:0];
  501. always @(posedge INKR_20_E) {INKR4[20], INKR3[20], INKR2[20], INKR1[20], INKR0[20]} <= D[4:0];
  502. always @(posedge INKR_21_E) {INKR4[21], INKR3[21], INKR2[21], INKR1[21], INKR0[21]} <= D[4:0];
  503. always @(posedge INKR_22_E) {INKR4[22], INKR3[22], INKR2[22], INKR1[22], INKR0[22]} <= D[4:0];
  504. always @(posedge INKR_23_E) {INKR4[23], INKR3[23], INKR2[23], INKR1[23], INKR0[23]} <= D[4:0];
  505. always @(posedge INKR_24_E) {INKR4[24], INKR3[24], INKR2[24], INKR1[24], INKR0[24]} <= D[4:0];
  506. always @(posedge INKR_25_E) {INKR4[25], INKR3[25], INKR2[25], INKR1[25], INKR0[25]} <= D[4:0];
  507. always @(posedge INKR_26_E) {INKR4[26], INKR3[26], INKR2[26], INKR1[26], INKR0[26]} <= D[4:0];
  508. always @(posedge INKR_27_E) {INKR4[27], INKR3[27], INKR2[27], INKR1[27], INKR0[27]} <= D[4:0];
  509. always @(posedge INKR_28_E) {INKR4[28], INKR3[28], INKR2[28], INKR1[28], INKR0[28]} <= D[4:0];
  510. always @(posedge INKR_29_E) {INKR4[29], INKR3[29], INKR2[29], INKR1[29], INKR0[29]} <= D[4:0];
  511. always @(posedge INKR_30_E) {INKR4[30], INKR3[30], INKR2[30], INKR1[30], INKR0[30]} <= D[4:0];
  512. always @(posedge INKR_31_E) {INKR4[31], INKR3[31], INKR2[31], INKR1[31], INKR0[31]} <= D[4:0];
  513. */
  514.  
  515. endmodule
  516.  
  517.  
  518.  
  519. // PDF page 6...
  520. module rom_ram_mapping (
  521.     input LROMEN,
  522.     input A15,
  523.     input A14,
  524.     input HROMEN,
  525.     input MREQ_N,
  526.     input RD_N,
  527.    
  528.     output ROMEN_N,
  529.     output RAMRD_N
  530. );
  531.  
  532. wire U601 = !LROMEN & !A15 & !A14;
  533.  
  534. wire U602 = A15 & A14 & !HROMEN;
  535.  
  536. wire ROM = U601 | U602; // U603
  537.  
  538. assign ROMEN_N = !ROM | MREQ_N | RD_N;  // U604.
  539.  
  540. assign RAMRD_N = ROM | MREQ_N | RD_N;       // U605.
  541.  
  542. endmodule
  543.  
  544.  
  545.  
  546. // PDF page 7...
  547. module cas_generation (
  548.     input RESET,
  549.     input M1_N,
  550.     input PHI_N,
  551.     input MREQ_N,
  552.     input S0,
  553.     input S1,
  554.     input S2,
  555.     input S3,
  556.     input S4,
  557.     input S5,
  558.     input S6,
  559.     input S7,
  560.    
  561.     input CLK_16M_N,
  562.    
  563.     output CAS_N
  564. );
  565.  
  566. reg U705_REG;
  567. always @(posedge PHI_N) U705_REG <= M1_N;
  568.  
  569.  
  570. wire U707 = !M1_N | U705_REG;
  571.  
  572. reg U708_REG;
  573. always @(posedge MREQ_N)
  574.     if (!U707) U708_REG <= 1'b0;    // Reset.
  575.     else U708_REG <= 1'b1;          // Else, Clock in a "1".
  576.  
  577.    
  578. wire U701 = !S4 & S5;
  579. wire U702 = !S3 & S1;
  580. wire U703 = S1 & S7;
  581.  
  582. wire U704 = U701 | U702 | U703;
  583.  
  584. reg U706_REG;
  585. always @(posedge CLK_16M_N) U706_REG <= U704;
  586.  
  587. reg U709_REG;
  588. always @(posedge CLK_16M_N) U709_REG <= U706_REG;
  589.  
  590.  
  591. wire U710 = !U708_REG | MREQ_N | !S5 | S5;
  592.  
  593. wire U711 = U706_REG | U712;
  594.  
  595. wire U712 = U710 & S2 & U711;
  596.  
  597. assign CAS_N = U712 | U706_REG | U709_REG;      // U713.
  598.  
  599.  
  600. endmodule
  601.  
  602.  
  603.  
  604. // PDF Page 8...
  605. module sync_gen (
  606.     input HSYNC,
  607.     input CCLK,
  608.     input RESET,
  609.     input VSYNC,
  610.     input IORQ_N,
  611.     input M1_N,
  612.     input IRQ_RESET,
  613.    
  614.     output NSYNC,
  615.     output MODE_SYNC,
  616.     output [4:2] HCNT,
  617.    
  618.     output INT_N
  619. );
  620.  
  621.  
  622. wire U807 = INTCNT[2] & INTCNT[4] & INTCNT[5];
  623. wire U811 = U807 | U816;
  624. wire U816 = U801 & U811;
  625.  
  626. wire U806 = !HCNT[2] & !HCNT[3] & !HCNT[4];
  627.  
  628. reg U812_REG;
  629. always @(posedge CCLK) U812_REG <= U806;
  630.  
  631. wire U817 = U806 & !U812_REG;
  632.  
  633. wire U831 = U816 | U817 | IRQ_RESET;
  634.  
  635. wire U801 = !HSYNC;
  636. wire U804 = U801 & U824_REG;
  637.  
  638.  
  639. // INTCNT [045] Register...
  640. reg [5:0] INTCNT;
  641.  
  642. wire INTCNT1_CLK = !INTCNT[0];
  643. wire INTCNT2_CLK = !INTCNT[1];
  644. wire INTCNT3_CLK = !INTCNT[2];
  645. wire INTCNT4_CLK = !INTCNT[3];
  646. wire INTCNT5_CLK = !INTCNT[4];
  647.  
  648. always @(posedge U801) if (U831) INTCNT[0] <= 1'b0; else INTCNT[0] <= !INTCNT[0];               // U815 reg.
  649. always @(posedge INTCNT1_CLK) if (U831) INTCNT[1] <= 1'b0; else INTCNT[1] <= !INTCNT[1];            // U821 reg.
  650. always @(posedge INTCNT2_CLK) if (U831) INTCNT[2] <= 1'b0; else INTCNT[2] <= !INTCNT[2];            // U826 reg.
  651. always @(posedge INTCNT3_CLK) if (U831) INTCNT[3] <= 1'b0; else INTCNT[3] <= !INTCNT[3];            // U830 reg.
  652. always @(posedge INTCNT4_CLK) if (U831) INTCNT[4] <= 1'b0; else INTCNT[4] <= !INTCNT[4];            // U832 reg.
  653. always @(posedge INTCNT5_CLK) if (U831 | U827) INTCNT[5] <= 1'b0; else INTCNT[5] <= !INTCNT[5]; // U835 reg.
  654.  
  655. wire U822 = !VSYNC;
  656.  
  657.  
  658. // HSYNC? Reg...
  659. reg U808_REG;
  660. reg U813_REG;
  661. reg U818_REG;
  662. reg U824_REG;
  663.  
  664. wire U813_CLK = !U808_REG;
  665. wire U818_CLK = !U813_REG;
  666. wire U824_CLK = !U818_REG;
  667.  
  668. always @(posedge CCLK) if (U804) U808_REG <= 1'b0; else U808_REG <= !U808_REG;
  669. always @(posedge U813_CLK) if (U804) U813_REG <= 1'b0; else U813_REG <= !U813_REG;
  670. always @(posedge U818_CLK) if (U804) U818_REG <= 1'b0; else U818_REG <= !U818_REG;
  671. always @(posedge U824_CLK) if (U822) U824_REG <= 1'b0; else U824_REG <= !U824_REG; // !VSYNC (U822) resets this reg.
  672.  
  673. wire U828 = U806 ^ U818_REG;
  674. assign NSYNC = U828;    // NSYNC, not "HSYNC". ;)
  675.  
  676. assign MODE_SYNC = !U818_REG;
  677.  
  678.  
  679. // HCNT reg...
  680. wire U802 = HCNT[2] & HCNT[2] & HCNT[4];
  681. wire U805 = RESET | U802;
  682.  
  683. reg U803_REG;
  684. always @(posedge CCLK) U803_REG <= VSYNC;
  685.  
  686. wire U810 = VSYNC & !U803_REG;
  687.  
  688. reg U809_REG;
  689. reg U814_REG;
  690. reg U820_REG;
  691. reg U825_REG;
  692. reg U829_REG;
  693.  
  694. wire U814_CLK = !U809_REG;
  695. wire U820_CLK = !U814_REG;
  696. wire U825_CLK = !U820_REG;
  697. wire U829_CLK = !U825_REG;
  698.  
  699. always @(posedge U801) if (U805) U809_REG <= 1'b0; else U809_REG <= !U809_REG;  // U809_REG
  700. always @(posedge U814_CLK) if (U810) U814_REG <= 1'b0; else  U814_REG <= !U814_REG; // U814_REG
  701. always @(posedge U820_CLK) if (U810) U820_REG <= 1'b0; else  U820_REG <= !U820_REG; // U820_REG
  702. always @(posedge U825_CLK) if (U810) U825_REG <= 1'b0; else  U825_REG <= !U825_REG; // U825_REG
  703. always @(posedge U829_CLK) if (U810) U829_REG <= 1'b0; else  U829_REG <= !U829_REG; // U829_REG
  704.  
  705.  
  706. assign HCNT[4] = U829_REG;
  707. assign HCNT[3] = U825_REG;
  708. assign HCNT[2] = U820_REG;
  709.  
  710.  
  711. // IRQACK_RST...
  712. wire U819 = ! (INT_N | IORQ_N | M1_N);
  713. wire U823 = U827 | U819;
  714. wire U827 = U823 & !M1_N;
  715.  
  716. wire U834 = U827 | IRQ_RESET;
  717.  
  718.  
  719. // INTerrupt output reg...
  720. wire U836_CLK = !INTCNT[5];
  721.  
  722. reg U836_REG;
  723. always @(posedge U836_CLK) if (U834) U836_REG <= 1'b0; else U836_REG <= 1'b1;
  724.  
  725. wire U837 = !U836_REG;
  726. assign INT_N = U837;
  727.  
  728. endmodule
  729.  
  730.  
  731.  
  732. // PDF page 9...
  733. module video_buffer (
  734.     input DISPEN,
  735.     input S3,
  736.     input CAS_N_IN,
  737.     input [7:0] D,
  738.    
  739.     output reg DISPEN_BUF,
  740.    
  741.     output reg [7:0] VIDEO_BUF
  742. );
  743.  
  744. wire U901 = S3 | CAS_N_IN;
  745.  
  746. always @(posedge U901) DISPEN_BUF <= DISPEN;
  747. always @(posedge U901) VIDEO_BUF <= D;
  748.  
  749. endmodule
  750.  
  751.  
  752.  
  753. // PDF page 10...
  754. module video_control (
  755.     input CLK_16M_N,
  756.     input DISPEN_BUF,
  757.     input S5,
  758.     input S6,
  759.     input PHI_N,
  760.     input [1:0] MODE,
  761.     input MODE_SYNC,
  762.    
  763.     output LOAD,
  764.     output reg COLOUR_KEEP,
  765.     output reg INK_SEL,
  766.     output reg BORDER_SEL,
  767.     output reg SHIFT,
  768.     output reg KEEP,
  769.    
  770.     output MODE_IS_2,
  771.     output MODE_IS_0
  772. );
  773.  
  774.  
  775. reg U1005_REG;
  776. always @(posedge CLK_16M_N) U1005_REG <= U1008;
  777.  
  778. wire U1008 = (U1006_REG) ? DISPEN_BUF : U1005_REG;
  779.  
  780.  
  781. wire U1001 = S5 ^ S6;
  782.  
  783. reg U1006_REG;
  784. always @(posedge CLK_16M_N) U1006_REG <= U1001;
  785.  
  786. assign LOAD = U1006_REG;
  787.  
  788.  
  789. wire U1002 = !PHI_N;
  790.  
  791. reg U1007_REG;
  792. always @(posedge CLK_16M_N) U1007_REG <= U1002;
  793.  
  794.  
  795. wire U1012 = !U1013_REG | U1006_REG;
  796.  
  797. reg U1013_REG;
  798. always @(posedge CLK_16M_N) U1013_REG <= U1012;
  799.  
  800.  
  801. wire U1016 = U1013_REG | MODE_IS_2;
  802. wire U1018 = !U1016;
  803. wire U1019 = U1008 & U1016;
  804. wire U1020 = !U1008 & U1016;
  805.  
  806.  
  807. wire U1014 = U1007_REG & U1013_REG;
  808. wire U1015 = U1013_REG & MODE_IS_1;
  809. wire U1017 = MODE_IS_2 | U1014 | U1015;
  810.  
  811. wire U1021 = !U1001 & U1017;
  812. wire U1022 = !U1017;
  813.  
  814.  
  815. always @(posedge CLK_16M_N) COLOUR_KEEP <= U1018;   // Reg U1023
  816. always @(posedge CLK_16M_N) INK_SEL     <= U1019;   // Reg U1024
  817. always @(posedge CLK_16M_N) BORDER_SEL  <= U1020;   // Reg U1025
  818. always @(posedge CLK_16M_N) SHIFT       <= U1021;   // Reg U1026
  819. always @(posedge CLK_16M_N) KEEP        <= U1022;   // Reg U1027
  820.  
  821.  
  822. reg U1003_REG;
  823. always @(posedge MODE_SYNC) U1003_REG <= MODE[0];
  824.  
  825. reg U1004_REG;
  826. always @(posedge MODE_SYNC) U1004_REG <= MODE[1];
  827.  
  828. assign MODE_IS_2 = !U1003_REG & U1004_REG;
  829. wire MODE_IS_1 = U1003_REG & !U1004_REG;
  830. assign MODE_IS_0 = !U1003_REG & !U1004_REG;
  831.  
  832.  
  833. endmodule
  834.  
  835.  
  836.  
  837. // PDF page 11...
  838. module video_shift (
  839.     input [7:0] VIDEO,
  840.     input KEEP,
  841.     input LOAD,
  842.     input SHIFT,
  843.    
  844.     input CLK_16M_N,
  845.    
  846.     output [3:0] CIDX
  847. );
  848.  
  849. // Bit 0...
  850. wire U1101 = SHIFT & 1'b0; // (Grounded input?)
  851. wire U1102 = LOAD & VIDEO[0];
  852. wire U1105 = KEEP & U1104_REG;
  853.  
  854. wire U1103 = U1101 | U1102 | U1105;
  855.  
  856. reg U1104_REG;
  857. always @(posedge CLK_16M_N) U1104_REG <= U1103;
  858.  
  859. // Bit 1...
  860. wire U1106 = SHIFT & U1104_REG; // Input from previous bit reg.
  861. wire U1107 = LOAD & VIDEO[1];
  862. wire U1110 = KEEP & U1104_REG;
  863.  
  864. wire U1108 = U1106 | U1107 | U1110;
  865.  
  866. reg U1109_REG;
  867. always @(posedge CLK_16M_N) U1109_REG <= U1108;
  868.  
  869. // Bit 2...
  870. wire U1111 = SHIFT & U1109_REG; // Input from previous bit reg.
  871. wire U1112 = LOAD & VIDEO[2];
  872. wire U1115 = KEEP & U1104_REG;
  873.  
  874. wire U1113 = U1111 | U1112 | U1115;
  875.  
  876. reg U1114_REG;
  877. always @(posedge CLK_16M_N) U1114_REG <= U1113;
  878.  
  879. // Bit 3...
  880. wire U1116 = SHIFT & U1114_REG; // Input from previous bit reg.
  881. wire U1117 = LOAD & VIDEO[3];
  882. wire U1120 = KEEP & U1104_REG;
  883.  
  884. wire U1118 = U1116 | U1117 | U1120;
  885.  
  886. reg U1119_REG;
  887. always @(posedge CLK_16M_N) U1119_REG <= U1118;
  888.  
  889. // Bit 4...
  890. wire U1121 = SHIFT & U1119_REG; // Input from previous bit reg.
  891. wire U1122 = LOAD & VIDEO[4];
  892. wire U1125 = KEEP & U1104_REG;
  893.  
  894. wire U1123 = U1121 | U1122 | U1125;
  895.  
  896. reg U1124_REG;
  897. always @(posedge CLK_16M_N) U1124_REG <= U1123;
  898.  
  899. // Bit 5...
  900. wire U1126 = SHIFT & U1124_REG; // Input from previous bit reg.
  901. wire U1127 = LOAD & VIDEO[5];
  902. wire U1130 = KEEP & U1104_REG;
  903.  
  904. wire U1128 = U1126 | U1127 | U1130;
  905.  
  906. reg U1129_REG;
  907. always @(posedge CLK_16M_N) U1129_REG <= U1128;
  908.  
  909. // Bit 6...
  910. wire U1131 = SHIFT & U1129_REG; // Input from previous bit reg.
  911. wire U1132 = LOAD & VIDEO[6];
  912. wire U1135 = KEEP & U1104_REG;
  913.  
  914. wire U1133 = U1131 | U1132 | U1135;
  915.  
  916. reg U1134_REG;
  917. always @(posedge CLK_16M_N) U1134_REG <= U1133;
  918.  
  919. // Bit 7...
  920. wire U1136 = SHIFT & U1134_REG; // Input from previous bit reg.
  921. wire U1137 = LOAD & VIDEO[7];
  922. wire U1140 = KEEP & U1104_REG;
  923.  
  924. wire U1138 = U1136 | U1137 | U1140;
  925.  
  926. reg U1139_REG;
  927. always @(posedge CLK_16M_N) U1139_REG <= U1138;
  928.  
  929.  
  930. endmodule
  931.  
  932.  
  933.  
  934. // PDF page 12...
  935. module colour_mux_full (
  936.     input [4:0] BORDER,
  937.    
  938.     input [15:0] INKR4,
  939.     input [15:0] INKR3,
  940.     input [15:0] INKR2,
  941.     input [15:0] INKR1,
  942.     input [15:0] INKR0,
  943.    
  944.     input COLOUR_KEEP,
  945.     input INK_SEL,
  946.     input BORDER_SEL,
  947.     input MODE_IS_0,
  948.     input MODE_IS_2,
  949.     input [3:0] CIDX,
  950.    
  951.     input CLK_16M_N,
  952.    
  953.     output [4:0] COLOUR
  954. );
  955.  
  956.  
  957. colour_mux_bit colour_mux_bit_4
  958. (
  959.     .CLK_16M_N(CLK_16M_N) , // input  CLK_16M_N
  960.     .COLOUR_KEEP(COLOUR_KEEP) , // input  COLOUR_KEEP
  961.     .BORDER_SEL(BORDER_SEL) ,   // input  BORDER_SEL
  962.     .BORDER(BORDER[4]) ,    // input  BORDER
  963.     .INK_SEL(INK_SEL) , // input  INK_SEL
  964.     .INKR(INKR4) ,  // input [15:0] INKR
  965.     .CIDX(CIDX) ,       // input [3:0] CIDX
  966.     .MODE_IS_0(MODE_IS_0) , // input  MODE_IS_0
  967.     .MODE_IS_2(MODE_IS_2) , // input  MODE_IS_2
  968.     .INK(COLOUR[4])     // output  INK
  969. );
  970.  
  971. colour_mux_bit colour_mux_bit_3
  972. (
  973.     .CLK_16M_N(CLK_16M_N) , // input  CLK_16M_N
  974.     .COLOUR_KEEP(COLOUR_KEEP) , // input  COLOUR_KEEP
  975.     .BORDER_SEL(BORDER_SEL) ,   // input  BORDER_SEL
  976.     .BORDER(BORDER[3]) ,    // input  BORDER
  977.     .INK_SEL(INK_SEL) , // input  INK_SEL
  978.     .INKR(INKR3) ,  // input [15:0] INKR
  979.     .CIDX(CIDX) ,       // input [3:0] CIDX
  980.     .MODE_IS_0(MODE_IS_0) , // input  MODE_IS_0
  981.     .MODE_IS_2(MODE_IS_2) , // input  MODE_IS_2
  982.     .INK(COLOUR[3])     // output  INK
  983. );
  984.  
  985. colour_mux_bit colour_mux_bit_2
  986. (
  987.     .CLK_16M_N(CLK_16M_N) , // input  CLK_16M_N
  988.     .COLOUR_KEEP(COLOUR_KEEP) , // input  COLOUR_KEEP
  989.     .BORDER_SEL(BORDER_SEL) ,   // input  BORDER_SEL
  990.     .BORDER(BORDER[2]) ,    // input  BORDER
  991.     .INK_SEL(INK_SEL) , // input  INK_SEL
  992.     .INKR(INKR2) ,  // input [15:0] INKR
  993.     .CIDX(CIDX) ,       // input [3:0] CIDX
  994.     .MODE_IS_0(MODE_IS_0) , // input  MODE_IS_0
  995.     .MODE_IS_2(MODE_IS_2) , // input  MODE_IS_2
  996.     .INK(COLOUR[2])     // output  INK
  997. );
  998.  
  999. colour_mux_bit colour_mux_bit_1
  1000. (
  1001.     .CLK_16M_N(CLK_16M_N) , // input  CLK_16M_N
  1002.     .COLOUR_KEEP(COLOUR_KEEP) , // input  COLOUR_KEEP
  1003.     .BORDER_SEL(BORDER_SEL) ,   // input  BORDER_SEL
  1004.     .BORDER(BORDER[1]) ,    // input  BORDER
  1005.     .INK_SEL(INK_SEL) , // input  INK_SEL
  1006.     .INKR(INKR1) ,  // input [15:0] INKR
  1007.     .CIDX(CIDX) ,       // input [3:0] CIDX
  1008.     .MODE_IS_0(MODE_IS_0) , // input  MODE_IS_0
  1009.     .MODE_IS_2(MODE_IS_2) , // input  MODE_IS_2
  1010.     .INK(COLOUR[1])     // output  INK
  1011. );
  1012.  
  1013. colour_mux_bit colour_mux_bit_0
  1014. (
  1015.     .CLK_16M_N(CLK_16M_N) , // input  CLK_16M_N
  1016.     .COLOUR_KEEP(COLOUR_KEEP) , // input  COLOUR_KEEP
  1017.     .BORDER_SEL(BORDER_SEL) ,   // input  BORDER_SEL
  1018.     .BORDER(BORDER[0]) ,    // input  BORDER
  1019.     .INK_SEL(INK_SEL) , // input  INK_SEL
  1020.     .INKR(INKR0) ,  // input [15:0] INKR
  1021.     .CIDX(CIDX) ,       // input [3:0] CIDX
  1022.     .MODE_IS_0(MODE_IS_0) , // input  MODE_IS_0
  1023.     .MODE_IS_2(MODE_IS_2) , // input  MODE_IS_2
  1024.     .INK(COLOUR[0])     // output  INK
  1025. );
  1026.  
  1027.  
  1028. endmodule
  1029.  
  1030.  
  1031.  
  1032. // PDF Page 13,14,15,16,17...
  1033. // (all pages contain duplicates of this block).
  1034. //
  1035. module colour_mux_bit (
  1036.     input CLK_16M_N,
  1037.  
  1038.     input COLOUR_KEEP,
  1039.     input BORDER_SEL,
  1040.     input BORDER,
  1041.     input INK_SEL,
  1042.     input [15:0] INKR,
  1043.    
  1044.     input [3:0] CIDX,
  1045.    
  1046.     input MODE_IS_0,
  1047.     input MODE_IS_2,
  1048.    
  1049.     output reg INK
  1050. );
  1051.  
  1052. wire U1301 = CIDX[2] & MODE_IS_0;
  1053. wire U1302 = CIDX[3] & MODE_IS_0;
  1054. wire U1303 = CIDX[1] & !MODE_IS_2;
  1055.  
  1056. wire U1304 = !U1301;
  1057. wire U1317 = !U1303;
  1058.  
  1059.  
  1060. wire U1305 = (U1301 | INKR[7])  & (INKR[3] | U1304);
  1061. wire U1306 = (U1301 | INKR[15]) & (INKR[11] | U1304);
  1062. wire U1307 = (U1301 | INKR[5])  & (INKR[1] | U1304);
  1063. wire U1308 = (U1301 | INKR[13]) & (INKR[9] | U1304);
  1064. wire U1309 = (U1301 | INKR[6])  & (INKR[2] | U1304);
  1065. wire U1310 = (U1301 | INKR[14]) & (INKR[10] | U1304);
  1066. wire U1311 = (U1301 | INKR[4])  & (INKR[0] | U1304);
  1067. wire U1312 = (U1301 | INKR[12]) & (INKR[8] | U1304);
  1068.  
  1069.  
  1070. wire U1313 = (!U1302) ? U1305 : U1306;
  1071. wire U1314 = (!U1302) ? U1307 : U1308;
  1072. wire U1315 = (!U1302) ? U1309 : U1310;
  1073. wire U1316 = (!U1302) ? U1311 : U1312;
  1074.  
  1075. wire U1318 = (U1303 | U1313) & (U1314 | U1317);
  1076. wire U1319 = (U1303 | U1315) & (U1316 | U1317);
  1077.  
  1078. wire U1320 = INK_SEL & CIDX[0] & U1318;
  1079. wire U1321 = INK_SEL & CIDX[0] & U1319;
  1080.  
  1081. wire U1322 = INK & COLOUR_KEEP;
  1082. wire U1323 = BORDER_SEL & BORDER;
  1083.  
  1084. wire U1324 = U1322 | U1323 | U1320 | U1321;
  1085.  
  1086. always @(posedge CLK_16M_N) INK <= U1324;
  1087.  
  1088. endmodule
  1089.  
  1090.  
  1091.  
  1092. // PDF Page 18...
  1093. module colour_decode(
  1094.     input [4:2] HCNT,
  1095.     input HSYNC,
  1096.     input [4:0] COLOUR,
  1097.    
  1098.     input CLK_16M_N,
  1099.    
  1100.     output reg BLUE_OE_N,
  1101.     output reg BLUE,
  1102.    
  1103.     output reg GREEN_OE_N,
  1104.     output reg GREEN,
  1105.    
  1106.     output reg RED_OE_N,
  1107.     output reg RED
  1108. );
  1109.  
  1110.  
  1111. wire U1801 = HCNT[2] & HCNT[3] & HCNT[4];
  1112. wire U1809 = !U1801 | HSYNC;
  1113.  
  1114. wire U1802 = COLOUR[1] | COLOUR[2];
  1115. wire U1803 = COLOUR[3] | COLOUR[4];
  1116. wire U1810 = ! (U1802 & U1803);
  1117.  
  1118. wire U1804 = COLOUR[1] & COLOUR[2];
  1119. wire U1805 = COLOUR[1] | COLOUR[2] | COLOUR[3] | COLOUR[4];
  1120. wire U1806 = COLOUR[2] & !COLOUR[0];
  1121. wire U1811 = U1804 | !U1805;
  1122. wire U1812 = U1806 | COLOUR[1];
  1123.  
  1124.  
  1125. wire U1807 = COLOUR[4] & COLOUR[3];
  1126. wire U1808 = !COLOUR[4] & COLOUR[0];
  1127. wire U1813 = !U1805 | U1807;
  1128. wire U1814 = U1808 | COLOUR[3];
  1129.  
  1130.  
  1131. always @(posedge CLK_16M_N) if (U1809) BLUE_OE_N <= 1'b0; else BLUE_OE_N <= U1810;
  1132. always @(posedge CLK_16M_N) if (U1809) BLUE <= 1'b0; else BLUE <= COLOUR[0];
  1133.  
  1134. always @(posedge CLK_16M_N) if (U1809) GREEN_OE_N <= 1'b0; else GREEN_OE_N <= U1811;
  1135. always @(posedge CLK_16M_N) if (U1809) GREEN <= 1'b0; else GREEN <= U1812;
  1136.  
  1137. always @(posedge CLK_16M_N) if (U1809) RED_OE_N <= 1'b0; else RED_OE_N <= U1813;
  1138. always @(posedge CLK_16M_N) if (U1809) RED <= 1'b0; else RED <= U1814;
  1139.  
  1140.  
  1141. endmodule
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