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- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.STD_LOGIC_ARITH.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
- entity base is
- Port (
- -- Entradas
- b0 : in std_logic;
- b1 : in std_logic;
- b2 : in std_logic;
- b3 : in std_logic;
- -- Salidas
- a : out std_logic;
- b : out std_logic;
- c : out std_logic;
- d : out std_logic;
- e : out std_logic;
- f : out std_logic;
- g : out std_logic;
- dp : out std_logic
- );
- end base;
- architecture behavioral of base is
- begin
- a<=((not(b3) and b2 and not(b1) and not(b0)) or (not(b3) and not(b2) and not(b1) and b0));
- b<=((not(b3) and b2 and not(b1) and b0) or (b2 and b1 and not(b0)) or (b3 and b2 and not(b0)) or (b3 and b2 and b1));
- c<=((not(b3) and not(b2) and b1 and not(b0)) or (b3 and b2 and not(b0)) or (b3 and b2 and b1));
- d<=((not(b2) and not(b1) and b0) or (not(b3) and b2 and not(b1) and not(b0)) or (b2 and b1 and b0) or (b3 and not(b2) and b1 and not(b0)));
- e<=((not(b2) and not(b1) and b0) or (not(b3) and b0) or (not(b3) and b2 and not(b1)));
- f<=((not(b3) and not(b2) and b0) or (not(b3) and not(b2) and b1) or (not(b3) and b1 and b0));
- g<=((b3 and b2 and not(b1) and b0) or (not(b3) and b2 and b1 and b0) or (not(b3) and not(b2) and not(b1)));
- dp<=((not(b2) and not(b1)) or (not(b3)));
- end behavioral;
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