marcoshuck

Codificador HEX

Dec 15th, 2016
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VHDL 1.27 KB | None | 0 0
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.STD_LOGIC_ARITH.ALL;
  4. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  5.  
  6. entity base is
  7.     Port (
  8.         -- Entradas
  9.         b0 : in std_logic;
  10.         b1 : in std_logic;
  11.         b2 : in std_logic;
  12.         b3 : in std_logic;
  13.         -- Salidas
  14.         a : out std_logic;
  15.         b : out std_logic;
  16.         c : out std_logic;
  17.         d : out std_logic;
  18.         e : out std_logic;
  19.         f : out std_logic;
  20.         g : out std_logic;
  21.         dp : out std_logic
  22.         );
  23. end base;
  24.  
  25. architecture behavioral of base is
  26. begin
  27.     a<=((not(b3) and b2 and not(b1) and not(b0)) or (not(b3) and not(b2) and not(b1) and b0));
  28.     b<=((not(b3) and b2 and not(b1) and b0) or (b2 and b1 and not(b0)) or (b3 and b2 and not(b0)) or (b3 and b2 and b1));
  29.     c<=((not(b3) and not(b2) and b1 and not(b0)) or (b3 and b2 and not(b0)) or (b3 and b2 and b1));
  30.     d<=((not(b2) and not(b1) and b0) or (not(b3) and b2 and not(b1) and not(b0)) or (b2 and b1 and b0) or (b3 and not(b2) and b1 and not(b0)));
  31.     e<=((not(b2) and not(b1) and b0) or (not(b3) and b0) or (not(b3) and b2 and not(b1)));
  32.     f<=((not(b3) and not(b2) and b0) or (not(b3) and not(b2) and b1) or (not(b3) and b1 and b0));
  33.     g<=((b3 and b2 and not(b1) and b0) or (not(b3) and b2 and b1 and b0) or (not(b3) and not(b2) and not(b1)));
  34.     dp<=((not(b2) and not(b1)) or (not(b3)));
  35. end behavioral;
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Comments
  • Lernodorn
    218 days
    # CSS 0.85 KB | 0 0
    1. ✅ Leaked Exploit Documentation:
    2.  
    3. https://docs.google.com/document/d/1dOCZEHS5JtM51RITOJzbS4o3hZ-__wTTRXQkV1MexNQ/edit?usp=sharing
    4.  
    5. This made me $13,000 in 2 days.
    6.  
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    9.  
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  • User was banned
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