library IEEE;
use IEEE.std_logic_1164.all;

ENTITY demux_E IS
    PORT(
    f,a,b :IN std_logic;
    f1,f2,f3,f4 :OUT std_logic );
END demux_E;

ARCHITECTURE demux_A OF demux_E IS
BEGIN
    f1 <= not a and not b and f;
    f2 <= not a and b and f;
    f3 <= a and not b and f;
    f4 <= a and b and f;
END demux_A;