Dediu_1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; -- pentru operatii aritmetice
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Counter is
    PORT(
        CLK: IN std_logic;
        CE: IN std_logic;
        R_OUT: OUT std_logic_vector(15 downto 0));
end Counter;

architecture Behavioral of Counter is
begin
    NUMARATOR: process(CLK, CE)
        variable valoare: std_logic_vector(15 downto 0) := (others => '0'); -- facem tot numarul 0
    begin
        IF(CE = '1') THEN
            IF(RISING_EDGE(CLK)) THEN
                IF(valoare = x"FFFF") THEN
                    valoare := (others=>'0');
                ELSE
                    valoare := valoare + x"0001";
                END IF;
            END IF;
        END IF;

        R_OUT <= valoare; -- punem valoarea pe iesire
    end process NUMARATOR;
end Behavioral;