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-- Company:
-- Engineer:
--
-- Create Date:    11:36:51 05/21/2019
-- Design Name:
-- Module Name:    licznikmod4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity licznikmod4 is
    Port ( wejscie : in  STD_LOGIC;
           wyjscie : out  STD_LOGIC_VECTOR (1 downto 0));
end licznikmod4;

architecture Behavioral of licznikmod4 is
signal liczenie : std_logic_vector(1 downto 0):="00";

begin

    process (wejscie)
    begin
        if wejscie='1' and wejscie'event then
            if liczenie = "11" then
                liczenie <= "00";
            else
                liczenie <= liczenie + 1;
            end if;
        end if;
    end process;
wyjscie <= liczenie;
end Behavioral;