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- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
- use IEEE.STD_LOGIC_ARITH.ALL;
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx primitives in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
- entity z_54 is
- port(
- clk:in std_logic;
- --button:in std_logic;
- seg:out std_logic_vector(2 downto 0);
- anode: out std_logic_vector(3 downto 0) := "1110";
- segpom: out std_logic_vector(4 downto 0) := "11111";
- led:out std_logic_vector(1 downto 0)
- );
- end z_54;
- architecture Behavioral of z_54 is
- signal clk_final:std_logic;
- begin
- s1:entity work.freq_div generic map(100_000_000)port map(clk, clk_final);
- process(clk_final)
- variable counter:integer range 0 to 68 := 0;
- begin
- if(clk_final'event and clk_final = '1') then
- counter := counter + 1;
- end if;
- --crveno--
- if(counter < 32) then
- seg <= "110";
- led <= "10";
- --crveno i žuto--
- elsif(counter = 32) then
- seg <= "100";
- led <= "01";
- --zeleno--
- elsif(counter < 65 and counter > 32) then
- seg <= "011";
- led <= "01";
- --žuto--
- elsif(counter = 65) then
- seg <= "101";
- led <= "01";
- elsif(counter > 65) then
- counter := 0;
- else
- anode <= "1110";
- end if;
- --if(button = '1' and counter > 32) then
- -- counter := 60;
- --end if;
- end process;
- end Behavioral;
- --------------------------------------------------------
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
- use IEEE.STD_LOGIC_ARITH.ALL;
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx primitives in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
- entity freq_div is
- generic(nfclk:natural:=100_000_000);
- port(
- clk:in std_logic;
- clk_final:buffer std_logic
- );
- end freq_div;
- architecture Behavioral of freq_div is
- begin
- process(clk)
- variable temp:integer range 0 to nfclk/2:=0;
- begin
- if(clk'event and clk='1')then
- temp:=temp+1;
- if(temp>=nfclk/2)then
- clk_final<=not clk_final;
- temp:=0;
- end if;
- end if;
- end process;
- end Behavioral;
- ---------------------------------------
- NET "clk" LOC = V10;
- NET "seg[0]" LOC = T17;
- NET "seg[1]" LOC = L14;
- NET "seg[2]" LOC = U18;
- NET "led[0]" LOC = U16;
- NET "led[1]" LOC = V16;
- NET "anode[0]" LOC = N16;
- NET "anode[1]" LOC = N15;
- NET "anode[2]" LOC = P18;
- NET "anode[3]" LOC = P17;
- NET "segpom[0]" LOC = T18;
- NET "segpom[1]" LOC = U17;
- NET "segpom[2]" LOC = M14;
- NET "segpom[3]" LOC = N14;
- NET "segpom[4]" LOC = M13;
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