Sistema de votos

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity base is
    Port (
        led_green : out std_logic;
        led_yellow : out std_logic;
        led_red : out std_logic;

        A : in std_logic;
        B : in std_logic;
        C : in std_logic;
        D : in std_logic;
        );
end base;

architecture behavioral of base is
begin
    led_green<=((B and C and D) or (A and C and D) or (A and B and D) or (A and B and C));
    led_red<=((not(B) and not(C) and not(D)) or (not(A) and not(C) and not(D)) or (not(A) and not(B) and not(D)) or (not(A) and not(B) and not(C)));
    led_yellow<=((A and B and not(C) and not(D)) or (A and not(B) and C and not(D)) or (A and not(B) and not(C) and D) or (not(A) and B and C and not(D)) or (not(A) and B and not(C) and D) or (not(A) and not(B) and C and D));
    --led_yellow<=(led_green nor led_red);
end behavioral;