20150114_KUAS_Verilog_FullAdder_4bit

module FullAdder_4bit(in1, in2, inCarry, sum, outCarry);
    input   [3:0] in1, in2;
    input   inCarry;
    output  [3:0] sum;
    output  outCarry;

    wire    [3:0] _wire; //be a temp for [2:0] bit carry
    FullAdder tmp1(in1[0], in2[0], inCarry, sum[0], _wire[0]);
    FullAdder tmp2(in1[1], in2[1], _wire[0], sum[1], _wire[1]);
    FullAdder tmp3(in1[2], in2[2], _wire[1], sum[2], _wire[2]);
    FullAdder tmp4(in1[3], in2[3], _wire[2], sum[3], outCarry);

    /* if use assign:

       assign {outCarry, sum} = in1 + in2 + inCarry; */
endmodule

module FullAdder(in1, in2, inCarry, sum, outCarry);
    input   in1, in2, inCarry;
    output  sum, outCarry;

    wire    w1, w2, w3;
    HalfAdder tmp1(inCarry, in1, w1, w2);
    HalfAdder tmp2(w1, in2, sum, w3);
    or  (outCarry, w2, w3);
endmodule

module HalfAdder(in1, in2, sum, carry);
    input   in1, in2;
    output  sum, carry;

    assign  {carry, sum} = in1 + in2;
endmodule