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DTS precompilado para OrangePi R1 Plus LTS

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Jan 23rd, 2025
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  1. # 0 "rk3328-orangepi-r1-plus-lts.dts"
  2. # 0 "<built-in>"
  3. # 0 "<command-line>"
  4. # 1 "rk3328-orangepi-r1-plus-lts.dts"
  5. # 9 "rk3328-orangepi-r1-plus-lts.dts"
  6. /dts-v1/;
  7. # 1 "rk3328-orangepi-r1-plus.dtsi" 1
  8.  
  9.  
  10.  
  11.  
  12.  
  13.  
  14. /dts-v1/;
  15.  
  16. # 1 "./dt-bindings/gpio/gpio.h" 1
  17. # 10 "rk3328-orangepi-r1-plus.dtsi" 2
  18. # 1 "./dt-bindings/leds/common.h" 1
  19. # 11 "rk3328-orangepi-r1-plus.dtsi" 2
  20. # 1 "rk3328.dtsi" 1
  21.  
  22.  
  23.  
  24.  
  25.  
  26. # 1 "./dt-bindings/clock/rk3328-cru.h" 1
  27. # 7 "rk3328.dtsi" 2
  28.  
  29. # 1 "./dt-bindings/interrupt-controller/arm-gic.h" 1
  30. # 9 "./dt-bindings/interrupt-controller/arm-gic.h"
  31. # 1 "./dt-bindings/interrupt-controller/irq.h" 1
  32. # 10 "./dt-bindings/interrupt-controller/arm-gic.h" 2
  33. # 9 "rk3328.dtsi" 2
  34.  
  35. # 1 "./dt-bindings/pinctrl/rockchip.h" 1
  36. # 11 "rk3328.dtsi" 2
  37. # 1 "./dt-bindings/power/rk3328-power.h" 1
  38. # 12 "rk3328.dtsi" 2
  39. # 1 "./dt-bindings/soc/rockchip,boot-mode.h" 1
  40. # 13 "rk3328.dtsi" 2
  41. # 1 "./dt-bindings/thermal/thermal.h" 1
  42. # 14 "rk3328.dtsi" 2
  43.  
  44. / {
  45.  compatible = "rockchip,rk3328";
  46.  
  47.  interrupt-parent = <&gic>;
  48.  #address-cells = <2>;
  49.  #size-cells = <2>;
  50.  
  51.  aliases {
  52.   gpio0 = &gpio0;
  53.   gpio1 = &gpio1;
  54.   gpio2 = &gpio2;
  55.   gpio3 = &gpio3;
  56.   serial0 = &uart0;
  57.   serial1 = &uart1;
  58.   serial2 = &uart2;
  59.   i2c0 = &i2c0;
  60.   i2c1 = &i2c1;
  61.   i2c2 = &i2c2;
  62.   i2c3 = &i2c3;
  63.  };
  64.  
  65.  cpus {
  66.   #address-cells = <2>;
  67.   #size-cells = <0>;
  68.  
  69.   cpu0: cpu@0 {
  70.    device_type = "cpu";
  71.    compatible = "arm,cortex-a53";
  72.    reg = <0x0 0x0>;
  73.    clocks = <&cru 6>;
  74.    #cooling-cells = <2>;
  75.    cpu-idle-states = <&CPU_SLEEP>;
  76.    dynamic-power-coefficient = <120>;
  77.    enable-method = "psci";
  78.    operating-points-v2 = <&cpu0_opp_table>;
  79.    i-cache-size = <0x8000>;
  80.    i-cache-line-size = <64>;
  81.    i-cache-sets = <256>;
  82.    d-cache-size = <0x8000>;
  83.    d-cache-line-size = <64>;
  84.    d-cache-sets = <128>;
  85.    next-level-cache = <&l2_cache>;
  86.   };
  87.  
  88.   cpu1: cpu@1 {
  89.    device_type = "cpu";
  90.    compatible = "arm,cortex-a53";
  91.    reg = <0x0 0x1>;
  92.    clocks = <&cru 6>;
  93.    #cooling-cells = <2>;
  94.    cpu-idle-states = <&CPU_SLEEP>;
  95.    dynamic-power-coefficient = <120>;
  96.    enable-method = "psci";
  97.    operating-points-v2 = <&cpu0_opp_table>;
  98.    i-cache-size = <0x8000>;
  99.    i-cache-line-size = <64>;
  100.    i-cache-sets = <256>;
  101.    d-cache-size = <0x8000>;
  102.    d-cache-line-size = <64>;
  103.    d-cache-sets = <128>;
  104.    next-level-cache = <&l2_cache>;
  105.   };
  106.  
  107.   cpu2: cpu@2 {
  108.    device_type = "cpu";
  109.    compatible = "arm,cortex-a53";
  110.    reg = <0x0 0x2>;
  111.    clocks = <&cru 6>;
  112.    #cooling-cells = <2>;
  113.    cpu-idle-states = <&CPU_SLEEP>;
  114.    dynamic-power-coefficient = <120>;
  115.    enable-method = "psci";
  116.    operating-points-v2 = <&cpu0_opp_table>;
  117.    i-cache-size = <0x8000>;
  118.    i-cache-line-size = <64>;
  119.    i-cache-sets = <256>;
  120.    d-cache-size = <0x8000>;
  121.    d-cache-line-size = <64>;
  122.    d-cache-sets = <128>;
  123.    next-level-cache = <&l2_cache>;
  124.   };
  125.  
  126.   cpu3: cpu@3 {
  127.    device_type = "cpu";
  128.    compatible = "arm,cortex-a53";
  129.    reg = <0x0 0x3>;
  130.    clocks = <&cru 6>;
  131.    #cooling-cells = <2>;
  132.    cpu-idle-states = <&CPU_SLEEP>;
  133.    dynamic-power-coefficient = <120>;
  134.    enable-method = "psci";
  135.    operating-points-v2 = <&cpu0_opp_table>;
  136.    i-cache-size = <0x8000>;
  137.    i-cache-line-size = <64>;
  138.    i-cache-sets = <256>;
  139.    d-cache-size = <0x8000>;
  140.    d-cache-line-size = <64>;
  141.    d-cache-sets = <128>;
  142.    next-level-cache = <&l2_cache>;
  143.   };
  144.  
  145.   idle-states {
  146.    entry-method = "psci";
  147.  
  148.    CPU_SLEEP: cpu-sleep {
  149.     compatible = "arm,idle-state";
  150.     local-timer-stop;
  151.     arm,psci-suspend-param = <0x0010000>;
  152.     entry-latency-us = <120>;
  153.     exit-latency-us = <250>;
  154.     min-residency-us = <900>;
  155.    };
  156.   };
  157.  
  158.   l2_cache: l2-cache {
  159.    compatible = "cache";
  160.    cache-level = <2>;
  161.    cache-unified;
  162.    cache-size = <0x40000>;
  163.    cache-line-size = <64>;
  164.    cache-sets = <256>;
  165.   };
  166.  };
  167.  
  168.  cpu0_opp_table: opp-table-0 {
  169.   compatible = "operating-points-v2";
  170.   opp-shared;
  171.  
  172.   opp-408000000 {
  173.    opp-hz = /bits/ 64 <408000000>;
  174.    opp-microvolt = <950000>;
  175.    clock-latency-ns = <40000>;
  176.    opp-suspend;
  177.   };
  178.   opp-600000000 {
  179.    opp-hz = /bits/ 64 <600000000>;
  180.    opp-microvolt = <950000>;
  181.    clock-latency-ns = <40000>;
  182.   };
  183.   opp-816000000 {
  184.    opp-hz = /bits/ 64 <816000000>;
  185.    opp-microvolt = <1000000>;
  186.    clock-latency-ns = <40000>;
  187.   };
  188.   opp-1008000000 {
  189.    opp-hz = /bits/ 64 <1008000000>;
  190.    opp-microvolt = <1100000>;
  191.    clock-latency-ns = <40000>;
  192.   };
  193.   opp-1200000000 {
  194.    opp-hz = /bits/ 64 <1200000000>;
  195.    opp-microvolt = <1225000>;
  196.    clock-latency-ns = <40000>;
  197.   };
  198.   opp-1296000000 {
  199.    opp-hz = /bits/ 64 <1296000000>;
  200.    opp-microvolt = <1300000>;
  201.    clock-latency-ns = <40000>;
  202.   };
  203.  };
  204.  
  205.  analog_sound: analog-sound {
  206.   compatible = "simple-audio-card";
  207.   simple-audio-card,format = "i2s";
  208.   simple-audio-card,mclk-fs = <256>;
  209.   simple-audio-card,name = "Analog";
  210.   status = "disabled";
  211.  
  212.   simple-audio-card,cpu {
  213.    sound-dai = <&i2s1>;
  214.   };
  215.  
  216.   simple-audio-card,codec {
  217.    sound-dai = <&codec>;
  218.   };
  219.  };
  220.  
  221.  arm-pmu {
  222.   compatible = "arm,cortex-a53-pmu";
  223.   interrupts = <0 100 4>,
  224.         <0 101 4>,
  225.         <0 102 4>,
  226.         <0 103 4>;
  227.   interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  228.  };
  229.  
  230.  display_subsystem: display-subsystem {
  231.   compatible = "rockchip,display-subsystem";
  232.   ports = <&vop_out>;
  233.  };
  234.  
  235.  hdmi_sound: hdmi-sound {
  236.   compatible = "simple-audio-card";
  237.   simple-audio-card,format = "i2s";
  238.   simple-audio-card,mclk-fs = <128>;
  239.   simple-audio-card,name = "HDMI";
  240.   status = "disabled";
  241.  
  242.   simple-audio-card,cpu {
  243.    sound-dai = <&i2s0>;
  244.   };
  245.  
  246.   simple-audio-card,codec {
  247.    sound-dai = <&hdmi>;
  248.   };
  249.  };
  250.  
  251.  psci {
  252.   compatible = "arm,psci-1.0", "arm,psci-0.2";
  253.   method = "smc";
  254.  };
  255.  
  256.  timer {
  257.   compatible = "arm,armv8-timer";
  258.   interrupts = <1 13 ((((1 << (4)) - 1) << 8) | 8)>,
  259.         <1 14 ((((1 << (4)) - 1) << 8) | 8)>,
  260.         <1 11 ((((1 << (4)) - 1) << 8) | 8)>,
  261.         <1 10 ((((1 << (4)) - 1) << 8) | 8)>;
  262.  };
  263.  
  264.  xin24m: xin24m {
  265.   compatible = "fixed-clock";
  266.   #clock-cells = <0>;
  267.   clock-frequency = <24000000>;
  268.   clock-output-names = "xin24m";
  269.  };
  270.  
  271.  i2s0: i2s@ff000000 {
  272.   compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
  273.   reg = <0x0 0xff000000 0x0 0x1000>;
  274.   interrupts = <0 26 4>;
  275.   clocks = <&cru 41>, <&cru 311>;
  276.   clock-names = "i2s_clk", "i2s_hclk";
  277.   dmas = <&dmac 11>, <&dmac 12>;
  278.   dma-names = "tx", "rx";
  279.   #sound-dai-cells = <0>;
  280.   status = "disabled";
  281.  };
  282.  
  283.  i2s1: i2s@ff010000 {
  284.   compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
  285.   reg = <0x0 0xff010000 0x0 0x1000>;
  286.   interrupts = <0 27 4>;
  287.   clocks = <&cru 42>, <&cru 312>;
  288.   clock-names = "i2s_clk", "i2s_hclk";
  289.   dmas = <&dmac 14>, <&dmac 15>;
  290.   dma-names = "tx", "rx";
  291.   #sound-dai-cells = <0>;
  292.   status = "disabled";
  293.  };
  294.  
  295.  i2s2: i2s@ff020000 {
  296.   compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
  297.   reg = <0x0 0xff020000 0x0 0x1000>;
  298.   interrupts = <0 28 4>;
  299.   clocks = <&cru 43>, <&cru 313>;
  300.   clock-names = "i2s_clk", "i2s_hclk";
  301.   dmas = <&dmac 0>, <&dmac 1>;
  302.   dma-names = "tx", "rx";
  303.   #sound-dai-cells = <0>;
  304.   status = "disabled";
  305.  };
  306.  
  307.  spdif: spdif@ff030000 {
  308.   compatible = "rockchip,rk3328-spdif";
  309.   reg = <0x0 0xff030000 0x0 0x1000>;
  310.   interrupts = <0 29 4>;
  311.   clocks = <&cru 46>, <&cru 314>;
  312.   clock-names = "mclk", "hclk";
  313.   dmas = <&dmac 10>;
  314.   dma-names = "tx";
  315.   pinctrl-names = "default";
  316.   pinctrl-0 = <&spdifm2_tx>;
  317.   #sound-dai-cells = <0>;
  318.   status = "disabled";
  319.  };
  320.  
  321.  pdm: pdm@ff040000 {
  322.   compatible = "rockchip,pdm";
  323.   reg = <0x0 0xff040000 0x0 0x1000>;
  324.   clocks = <&cru 61>, <&cru 338>;
  325.   clock-names = "pdm_clk", "pdm_hclk";
  326.   dmas = <&dmac 16>;
  327.   dma-names = "rx";
  328.   pinctrl-names = "default", "sleep";
  329.   pinctrl-0 = <&pdmm0_clk
  330.         &pdmm0_sdi0
  331.         &pdmm0_sdi1
  332.         &pdmm0_sdi2
  333.         &pdmm0_sdi3>;
  334.   pinctrl-1 = <&pdmm0_clk_sleep
  335.         &pdmm0_sdi0_sleep
  336.         &pdmm0_sdi1_sleep
  337.         &pdmm0_sdi2_sleep
  338.         &pdmm0_sdi3_sleep>;
  339.   status = "disabled";
  340.  };
  341.  
  342.  grf: syscon@ff100000 {
  343.   compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
  344.   reg = <0x0 0xff100000 0x0 0x1000>;
  345.  
  346.   io_domains: io-domains {
  347.    compatible = "rockchip,rk3328-io-voltage-domain";
  348.    status = "disabled";
  349.   };
  350.  
  351.   grf_gpio: gpio {
  352.    compatible = "rockchip,rk3328-grf-gpio";
  353.    gpio-controller;
  354.    #gpio-cells = <2>;
  355.   };
  356.  
  357.   power: power-controller {
  358.    compatible = "rockchip,rk3328-power-controller";
  359.    #power-domain-cells = <1>;
  360.    #address-cells = <1>;
  361.    #size-cells = <0>;
  362.  
  363.    power-domain@6 {
  364.     reg = <6>;
  365.     #power-domain-cells = <0>;
  366.    };
  367.    power-domain@5 {
  368.     reg = <5>;
  369.     clocks = <&cru 139>,
  370.       <&cru 322>,
  371.       <&cru 65>,
  372.       <&cru 66>;
  373.     #power-domain-cells = <0>;
  374.    };
  375.    power-domain@8 {
  376.     reg = <8>;
  377.     clocks = <&cru 143>, <&cru 326>;
  378.     #power-domain-cells = <0>;
  379.    };
  380.   };
  381.  
  382.   reboot-mode {
  383.    compatible = "syscon-reboot-mode";
  384.    offset = <0x5c8>;
  385.    mode-normal = <(0x5242C300 + 0)>;
  386.    mode-recovery = <(0x5242C300 + 3)>;
  387.    mode-bootloader = <(0x5242C300 + 9)>;
  388.    mode-loader = <(0x5242C300 + 1)>;
  389.   };
  390.  };
  391.  
  392.  uart0: serial@ff110000 {
  393.   compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
  394.   reg = <0x0 0xff110000 0x0 0x100>;
  395.   interrupts = <0 55 4>;
  396.   clocks = <&cru 38>, <&cru 210>;
  397.   clock-names = "baudclk", "apb_pclk";
  398.   dmas = <&dmac 2>, <&dmac 3>;
  399.   dma-names = "tx", "rx";
  400.   pinctrl-names = "default";
  401.   pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
  402.   reg-io-width = <4>;
  403.   reg-shift = <2>;
  404.   status = "disabled";
  405.  };
  406.  
  407.  uart1: serial@ff120000 {
  408.   compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
  409.   reg = <0x0 0xff120000 0x0 0x100>;
  410.   interrupts = <0 56 4>;
  411.   clocks = <&cru 39>, <&cru 211>;
  412.   clock-names = "baudclk", "apb_pclk";
  413.   dmas = <&dmac 4>, <&dmac 5>;
  414.   dma-names = "tx", "rx";
  415.   pinctrl-names = "default";
  416.   pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
  417.   reg-io-width = <4>;
  418.   reg-shift = <2>;
  419.   status = "disabled";
  420.  };
  421.  
  422.  uart2: serial@ff130000 {
  423.   compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
  424.   reg = <0x0 0xff130000 0x0 0x100>;
  425.   interrupts = <0 57 4>;
  426.   clocks = <&cru 40>, <&cru 212>;
  427.   clock-names = "baudclk", "apb_pclk";
  428.   dmas = <&dmac 6>, <&dmac 7>;
  429.   dma-names = "tx", "rx";
  430.   pinctrl-names = "default";
  431.   pinctrl-0 = <&uart2m1_xfer>;
  432.   reg-io-width = <4>;
  433.   reg-shift = <2>;
  434.   status = "disabled";
  435.  };
  436.  
  437.  i2c0: i2c@ff150000 {
  438.   compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
  439.   reg = <0x0 0xff150000 0x0 0x1000>;
  440.   interrupts = <0 36 4>;
  441.   #address-cells = <1>;
  442.   #size-cells = <0>;
  443.   clocks = <&cru 55>, <&cru 205>;
  444.   clock-names = "i2c", "pclk";
  445.   pinctrl-names = "default";
  446.   pinctrl-0 = <&i2c0_xfer>;
  447.   status = "disabled";
  448.  };
  449.  
  450.  i2c1: i2c@ff160000 {
  451.   compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
  452.   reg = <0x0 0xff160000 0x0 0x1000>;
  453.   interrupts = <0 37 4>;
  454.   #address-cells = <1>;
  455.   #size-cells = <0>;
  456.   clocks = <&cru 56>, <&cru 206>;
  457.   clock-names = "i2c", "pclk";
  458.   pinctrl-names = "default";
  459.   pinctrl-0 = <&i2c1_xfer>;
  460.   status = "disabled";
  461.  };
  462.  
  463.  i2c2: i2c@ff170000 {
  464.   compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
  465.   reg = <0x0 0xff170000 0x0 0x1000>;
  466.   interrupts = <0 38 4>;
  467.   #address-cells = <1>;
  468.   #size-cells = <0>;
  469.   clocks = <&cru 57>, <&cru 207>;
  470.   clock-names = "i2c", "pclk";
  471.   pinctrl-names = "default";
  472.   pinctrl-0 = <&i2c2_xfer>;
  473.   status = "disabled";
  474.  };
  475.  
  476.  i2c3: i2c@ff180000 {
  477.   compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
  478.   reg = <0x0 0xff180000 0x0 0x1000>;
  479.   interrupts = <0 39 4>;
  480.   #address-cells = <1>;
  481.   #size-cells = <0>;
  482.   clocks = <&cru 58>, <&cru 208>;
  483.   clock-names = "i2c", "pclk";
  484.   pinctrl-names = "default";
  485.   pinctrl-0 = <&i2c3_xfer>;
  486.   status = "disabled";
  487.  };
  488.  
  489.  spi0: spi@ff190000 {
  490.   compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
  491.   reg = <0x0 0xff190000 0x0 0x1000>;
  492.   interrupts = <0 49 4>;
  493.   #address-cells = <1>;
  494.   #size-cells = <0>;
  495.   clocks = <&cru 32>, <&cru 209>;
  496.   clock-names = "spiclk", "apb_pclk";
  497.   dmas = <&dmac 8>, <&dmac 9>;
  498.   dma-names = "tx", "rx";
  499.   pinctrl-names = "default";
  500.   pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
  501.   status = "disabled";
  502.  };
  503.  
  504.  wdt: watchdog@ff1a0000 {
  505.   compatible = "rockchip,rk3328-wdt", "snps,dw-wdt";
  506.   reg = <0x0 0xff1a0000 0x0 0x100>;
  507.   interrupts = <0 40 4>;
  508.   clocks = <&cru 236>;
  509.  };
  510.  
  511.  pwm0: pwm@ff1b0000 {
  512.   compatible = "rockchip,rk3328-pwm";
  513.   reg = <0x0 0xff1b0000 0x0 0x10>;
  514.   clocks = <&cru 60>, <&cru 214>;
  515.   clock-names = "pwm", "pclk";
  516.   pinctrl-names = "default";
  517.   pinctrl-0 = <&pwm0_pin>;
  518.   #pwm-cells = <3>;
  519.   status = "disabled";
  520.  };
  521.  
  522.  pwm1: pwm@ff1b0010 {
  523.   compatible = "rockchip,rk3328-pwm";
  524.   reg = <0x0 0xff1b0010 0x0 0x10>;
  525.   clocks = <&cru 60>, <&cru 214>;
  526.   clock-names = "pwm", "pclk";
  527.   pinctrl-names = "default";
  528.   pinctrl-0 = <&pwm1_pin>;
  529.   #pwm-cells = <3>;
  530.   status = "disabled";
  531.  };
  532.  
  533.  pwm2: pwm@ff1b0020 {
  534.   compatible = "rockchip,rk3328-pwm";
  535.   reg = <0x0 0xff1b0020 0x0 0x10>;
  536.   clocks = <&cru 60>, <&cru 214>;
  537.   clock-names = "pwm", "pclk";
  538.   pinctrl-names = "default";
  539.   pinctrl-0 = <&pwm2_pin>;
  540.   #pwm-cells = <3>;
  541.   status = "disabled";
  542.  };
  543.  
  544.  pwm3: pwm@ff1b0030 {
  545.   compatible = "rockchip,rk3328-pwm";
  546.   reg = <0x0 0xff1b0030 0x0 0x10>;
  547.   clocks = <&cru 60>, <&cru 214>;
  548.   clock-names = "pwm", "pclk";
  549.   pinctrl-names = "default";
  550.   pinctrl-0 = <&pwmir_pin>;
  551.   #pwm-cells = <3>;
  552.   status = "disabled";
  553.  };
  554.  
  555.  dmac: dma-controller@ff1f0000 {
  556.   compatible = "arm,pl330", "arm,primecell";
  557.   reg = <0x0 0xff1f0000 0x0 0x4000>;
  558.   interrupts = <0 0 4>,
  559.         <0 1 4>;
  560.   arm,pl330-periph-burst;
  561.   clocks = <&cru 134>;
  562.   clock-names = "apb_pclk";
  563.   #dma-cells = <1>;
  564.  };
  565.  
  566.  thermal-zones {
  567.   soc_thermal: soc-thermal {
  568.    polling-delay-passive = <20>;
  569.    polling-delay = <1000>;
  570.    sustainable-power = <1000>;
  571.  
  572.    thermal-sensors = <&tsadc 0>;
  573.  
  574.    trips {
  575.     threshold: trip-point0 {
  576.      temperature = <70000>;
  577.      hysteresis = <2000>;
  578.      type = "passive";
  579.     };
  580.     target: trip-point1 {
  581.      temperature = <85000>;
  582.      hysteresis = <2000>;
  583.      type = "passive";
  584.     };
  585.     soc_crit: soc-crit {
  586.      temperature = <95000>;
  587.      hysteresis = <2000>;
  588.      type = "critical";
  589.     };
  590.    };
  591.  
  592.    cooling-maps {
  593.     map0 {
  594.      trip = <&target>;
  595.      cooling-device = <&cpu0 (~0) (~0)>,
  596.         <&cpu1 (~0) (~0)>,
  597.         <&cpu2 (~0) (~0)>,
  598.         <&cpu3 (~0) (~0)>;
  599.      contribution = <4096>;
  600.     };
  601.    };
  602.   };
  603.  
  604.  };
  605.  
  606.  tsadc: tsadc@ff250000 {
  607.   compatible = "rockchip,rk3328-tsadc";
  608.   reg = <0x0 0xff250000 0x0 0x100>;
  609.   interrupts = <0 58 4>;
  610.   assigned-clocks = <&cru 36>;
  611.   assigned-clock-rates = <50000>;
  612.   clocks = <&cru 36>, <&cru 213>;
  613.   clock-names = "tsadc", "apb_pclk";
  614.   pinctrl-names = "init", "default", "sleep";
  615.   pinctrl-0 = <&otp_pin>;
  616.   pinctrl-1 = <&otp_out>;
  617.   pinctrl-2 = <&otp_pin>;
  618.   resets = <&cru 66>;
  619.   reset-names = "tsadc-apb";
  620.   rockchip,grf = <&grf>;
  621.   rockchip,hw-tshut-temp = <100000>;
  622.   #thermal-sensor-cells = <1>;
  623.   status = "disabled";
  624.  };
  625.  
  626.  efuse: efuse@ff260000 {
  627.   compatible = "rockchip,rk3328-efuse";
  628.   reg = <0x0 0xff260000 0x0 0x50>;
  629.   #address-cells = <1>;
  630.   #size-cells = <1>;
  631.   clocks = <&cru 62>;
  632.   clock-names = "pclk_efuse";
  633.   rockchip,efuse-size = <0x20>;
  634.  
  635.  
  636.   efuse_id: id@7 {
  637.    reg = <0x07 0x10>;
  638.   };
  639.   cpu_leakage: cpu-leakage@17 {
  640.    reg = <0x17 0x1>;
  641.   };
  642.   logic_leakage: logic-leakage@19 {
  643.    reg = <0x19 0x1>;
  644.   };
  645.   efuse_cpu_version: cpu-version@1a {
  646.    reg = <0x1a 0x1>;
  647.    bits = <3 3>;
  648.   };
  649.  };
  650.  
  651.  saradc: adc@ff280000 {
  652.   compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
  653.   reg = <0x0 0xff280000 0x0 0x100>;
  654.   interrupts = <0 80 4>;
  655.   #io-channel-cells = <1>;
  656.   clocks = <&cru 37>, <&cru 234>;
  657.   clock-names = "saradc", "apb_pclk";
  658.   resets = <&cru 86>;
  659.   reset-names = "saradc-apb";
  660.   status = "disabled";
  661.  };
  662.  
  663.  gpu: gpu@ff300000 {
  664.   compatible = "rockchip,rk3328-mali", "arm,mali-450";
  665.   reg = <0x0 0xff300000 0x0 0x30000>;
  666.   interrupts = <0 90 4>,
  667.         <0 87 4>,
  668.         <0 93 4>,
  669.         <0 88 4>,
  670.         <0 89 4>,
  671.         <0 91 4>,
  672.         <0 92 4>;
  673.   interrupt-names = "gp",
  674.       "gpmmu",
  675.       "pp",
  676.       "pp0",
  677.       "ppmmu0",
  678.       "pp1",
  679.       "ppmmu1";
  680.   clocks = <&cru 135>, <&cru 135>;
  681.   clock-names = "bus", "core";
  682.   resets = <&cru 102>;
  683.  };
  684.  
  685.  h265e_mmu: iommu@ff330200 {
  686.   compatible = "rockchip,iommu";
  687.   reg = <0x0 0xff330200 0 0x100>;
  688.   interrupts = <0 96 4>;
  689.   clocks = <&cru 147>, <&cru 221>;
  690.   clock-names = "aclk", "iface";
  691.   #iommu-cells = <0>;
  692.   status = "disabled";
  693.  };
  694.  
  695.  vepu_mmu: iommu@ff340800 {
  696.   compatible = "rockchip,iommu";
  697.   reg = <0x0 0xff340800 0x0 0x40>;
  698.   interrupts = <0 98 4>;
  699.   clocks = <&cru 143>, <&cru 326>;
  700.   clock-names = "aclk", "iface";
  701.   #iommu-cells = <0>;
  702.   status = "disabled";
  703.  };
  704.  
  705.  vpu: video-codec@ff350000 {
  706.   compatible = "rockchip,rk3328-vpu";
  707.   reg = <0x0 0xff350000 0x0 0x800>;
  708.   interrupts = <0 9 4>;
  709.   interrupt-names = "vdpu";
  710.   clocks = <&cru 143>, <&cru 326>;
  711.   clock-names = "aclk", "hclk";
  712.   iommus = <&vpu_mmu>;
  713.   power-domains = <&power 8>;
  714.  };
  715.  
  716.  vpu_mmu: iommu@ff350800 {
  717.   compatible = "rockchip,iommu";
  718.   reg = <0x0 0xff350800 0x0 0x40>;
  719.   interrupts = <0 11 4>;
  720.   clocks = <&cru 143>, <&cru 326>;
  721.   clock-names = "aclk", "iface";
  722.   #iommu-cells = <0>;
  723.   power-domains = <&power 8>;
  724.  };
  725.  
  726.  vdec: video-codec@ff360000 {
  727.   compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
  728.   reg = <0x0 0xff360000 0x0 0x480>;
  729.   interrupts = <0 7 4>;
  730.   clocks = <&cru 139>, <&cru 322>,
  731.     <&cru 65>, <&cru 66>;
  732.   clock-names = "axi", "ahb", "cabac", "core";
  733.   assigned-clocks = <&cru 139>, <&cru 65>,
  734.       <&cru 66>;
  735.   assigned-clock-rates = <400000000>, <400000000>, <300000000>;
  736.   iommus = <&vdec_mmu>;
  737.   power-domains = <&power 5>;
  738.  };
  739.  
  740.  vdec_mmu: iommu@ff360480 {
  741.   compatible = "rockchip,iommu";
  742.   reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
  743.   interrupts = <0 74 4>;
  744.   clocks = <&cru 139>, <&cru 322>;
  745.   clock-names = "aclk", "iface";
  746.   #iommu-cells = <0>;
  747.   power-domains = <&power 5>;
  748.  };
  749.  
  750.  vop: vop@ff370000 {
  751.   compatible = "rockchip,rk3328-vop";
  752.   reg = <0x0 0xff370000 0x0 0x3efc>;
  753.   interrupts = <0 32 4>;
  754.   clocks = <&cru 145>, <&cru 120>, <&cru 315>;
  755.   clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
  756.   resets = <&cru 133>, <&cru 134>, <&cru 135>;
  757.   reset-names = "axi", "ahb", "dclk";
  758.   iommus = <&vop_mmu>;
  759.   status = "disabled";
  760.  
  761.   vop_out: port {
  762.    #address-cells = <1>;
  763.    #size-cells = <0>;
  764.  
  765.    vop_out_hdmi: endpoint@0 {
  766.     reg = <0>;
  767.     remote-endpoint = <&hdmi_in_vop>;
  768.    };
  769.   };
  770.  };
  771.  
  772.  vop_mmu: iommu@ff373f00 {
  773.   compatible = "rockchip,iommu";
  774.   reg = <0x0 0xff373f00 0x0 0x100>;
  775.   interrupts = <0 32 4>;
  776.   clocks = <&cru 145>, <&cru 315>;
  777.   clock-names = "aclk", "iface";
  778.   #iommu-cells = <0>;
  779.   status = "disabled";
  780.  };
  781.  
  782.  hdmi: hdmi@ff3c0000 {
  783.   compatible = "rockchip,rk3328-dw-hdmi";
  784.   reg = <0x0 0xff3c0000 0x0 0x20000>;
  785.   reg-io-width = <4>;
  786.   interrupts = <0 35 4>;
  787.   clocks = <&cru 231>,
  788.     <&cru 70>,
  789.     <&cru 30>;
  790.   clock-names = "iahb",
  791.          "isfr",
  792.          "cec";
  793.   phys = <&hdmiphy>;
  794.   phy-names = "hdmi";
  795.   pinctrl-names = "default";
  796.   pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
  797.   rockchip,grf = <&grf>;
  798.   #sound-dai-cells = <0>;
  799.   status = "disabled";
  800.  
  801.   ports {
  802.    #address-cells = <1>;
  803.    #size-cells = <0>;
  804.  
  805.    hdmi_in: port@0 {
  806.     reg = <0>;
  807.  
  808.     hdmi_in_vop: endpoint {
  809.      remote-endpoint = <&vop_out_hdmi>;
  810.     };
  811.    };
  812.  
  813.    hdmi_out: port@1 {
  814.     reg = <1>;
  815.    };
  816.   };
  817.  };
  818.  
  819.  codec: codec@ff410000 {
  820.   compatible = "rockchip,rk3328-codec";
  821.   reg = <0x0 0xff410000 0x0 0x1000>;
  822.   clocks = <&cru 235>, <&cru 42>;
  823.   clock-names = "pclk", "mclk";
  824.   rockchip,grf = <&grf>;
  825.   #sound-dai-cells = <0>;
  826.   status = "disabled";
  827.  };
  828.  
  829.  hdmiphy: phy@ff430000 {
  830.   compatible = "rockchip,rk3328-hdmi-phy";
  831.   reg = <0x0 0xff430000 0x0 0x10000>;
  832.   interrupts = <0 83 4>;
  833.   clocks = <&cru 228>, <&xin24m>, <&cru 121>;
  834.   clock-names = "sysclk", "refoclk", "refpclk";
  835.   clock-output-names = "hdmi_phy";
  836.   #clock-cells = <0>;
  837.   nvmem-cells = <&efuse_cpu_version>;
  838.   nvmem-cell-names = "cpu-version";
  839.   #phy-cells = <0>;
  840.   status = "disabled";
  841.  };
  842.  
  843.  cru: clock-controller@ff440000 {
  844.   compatible = "rockchip,rk3328-cru";
  845.   reg = <0x0 0xff440000 0x0 0x1000>;
  846.   clocks = <&xin24m>;
  847.   clock-names = "xin24m";
  848.   rockchip,grf = <&grf>;
  849.   #clock-cells = <1>;
  850.   #reset-cells = <1>;
  851.   assigned-clocks =
  852.  
  853.  
  854.  
  855.  
  856.  
  857.  
  858.    <&cru 120>, <&cru 61>,
  859.    <&cru 30>, <&cru 38>,
  860.    <&cru 39>, <&cru 40>,
  861.    <&cru 136>, <&cru 137>,
  862.    <&cru 142>, <&cru 133>,
  863.    <&cru 131>, <&cru 138>,
  864.    <&cru 140>, <&cru 141>,
  865.    <&cru 65>, <&cru 66>,
  866.    <&cru 68>, <&cru 67>,
  867.    <&cru 34>, <&cru 92>,
  868.    <&cru 53>, <&cru 6>,
  869.    <&cru 4>, <&cru 3>,
  870.    <&cru 136>, <&cru 328>,
  871.    <&cru 216>, <&cru 137>,
  872.    <&cru 308>, <&cru 230>,
  873.    <&cru 30>;
  874.   assigned-clock-parents =
  875.    <&cru 122>, <&cru 1>,
  876.    <&cru 4>, <&xin24m>,
  877.    <&xin24m>, <&xin24m>;
  878.   assigned-clock-rates =
  879.    <0>, <61440000>,
  880.    <0>, <24000000>,
  881.    <24000000>, <24000000>,
  882.    <15000000>, <15000000>,
  883.    <300000000>, <100000000>,
  884.    <400000000>, <100000000>,
  885.    <50000000>, <100000000>,
  886.    <100000000>, <100000000>,
  887.    <50000000>, <50000000>,
  888.    <50000000>, <50000000>,
  889.    <24000000>, <600000000>,
  890.    <491520000>, <1200000000>,
  891.    <150000000>, <75000000>,
  892.    <75000000>, <150000000>,
  893.    <75000000>, <75000000>,
  894.    <32768>;
  895.  };
  896.  
  897.  usb2phy_grf: syscon@ff450000 {
  898.   compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
  899.         "simple-mfd";
  900.   reg = <0x0 0xff450000 0x0 0x10000>;
  901.   #address-cells = <1>;
  902.   #size-cells = <1>;
  903.  
  904.   u2phy: usb2phy@100 {
  905.    compatible = "rockchip,rk3328-usb2phy";
  906.    reg = <0x100 0x10>;
  907.    clocks = <&xin24m>;
  908.    clock-names = "phyclk";
  909.    clock-output-names = "usb480m_phy";
  910.    #clock-cells = <0>;
  911.    assigned-clocks = <&cru 123>;
  912.    assigned-clock-parents = <&u2phy>;
  913.    status = "disabled";
  914.  
  915.    u2phy_otg: otg-port {
  916.     #phy-cells = <0>;
  917.     interrupts = <0 59 4>,
  918.           <0 60 4>,
  919.           <0 61 4>;
  920.     interrupt-names = "otg-bvalid", "otg-id",
  921.         "linestate";
  922.     status = "disabled";
  923.    };
  924.  
  925.    u2phy_host: host-port {
  926.     #phy-cells = <0>;
  927.     interrupts = <0 62 4>;
  928.     interrupt-names = "linestate";
  929.     status = "disabled";
  930.    };
  931.   };
  932.  };
  933.  
  934.  sdmmc: mmc@ff500000 {
  935.   compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
  936.   reg = <0x0 0xff500000 0x0 0x4000>;
  937.   interrupts = <0 12 4>;
  938.   clocks = <&cru 317>, <&cru 33>,
  939.     <&cru 74>, <&cru 78>;
  940.   clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  941.   fifo-depth = <0x100>;
  942.   max-frequency = <150000000>;
  943.   resets = <&cru 109>;
  944.   reset-names = "reset";
  945.   status = "disabled";
  946.  };
  947.  
  948.  sdio: mmc@ff510000 {
  949.   compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
  950.   reg = <0x0 0xff510000 0x0 0x4000>;
  951.   interrupts = <0 13 4>;
  952.   clocks = <&cru 318>, <&cru 34>,
  953.     <&cru 75>, <&cru 79>;
  954.   clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  955.   fifo-depth = <0x100>;
  956.   max-frequency = <150000000>;
  957.   resets = <&cru 110>;
  958.   reset-names = "reset";
  959.   status = "disabled";
  960.  };
  961.  
  962.  emmc: mmc@ff520000 {
  963.   compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
  964.   reg = <0x0 0xff520000 0x0 0x4000>;
  965.   interrupts = <0 14 4>;
  966.   clocks = <&cru 319>, <&cru 35>,
  967.     <&cru 76>, <&cru 80>;
  968.   clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  969.   fifo-depth = <0x100>;
  970.   max-frequency = <150000000>;
  971.   resets = <&cru 111>;
  972.   reset-names = "reset";
  973.   status = "disabled";
  974.  };
  975.  
  976.  gmac2io: ethernet@ff540000 {
  977.   compatible = "rockchip,rk3328-gmac";
  978.   reg = <0x0 0xff540000 0x0 0x10000>;
  979.   interrupts = <0 24 4>;
  980.   interrupt-names = "macirq";
  981.   clocks = <&cru 100>, <&cru 87>,
  982.     <&cru 88>, <&cru 90>,
  983.     <&cru 89>, <&cru 150>,
  984.     <&cru 223>;
  985.   clock-names = "stmmaceth", "mac_clk_rx",
  986.               "mac_clk_tx", "clk_mac_ref",
  987.               "clk_mac_refout", "aclk_mac",
  988.               "pclk_mac";
  989.   assigned-clocks = <&cru 100>, <&cru 102>;
  990.   assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
  991.   clock_in_out = "input";
  992.  
  993.   rockchip,grf = <&grf>;
  994.   resets = <&cru 99>;
  995.   reset-names = "stmmaceth";
  996.  
  997.   rx-fifo-depth = <16384>;
  998.   tx-fifo-depth = <8192>;
  999.   #rx-fifo-size = <4096>;
  1000.   #tx-fifo-size = <4096>;
  1001.   #rx-fifo-size-gige = <16384>;
  1002.   #tx-fifo-size-gige = <8192>;
  1003.   snps,txpbl = <0x4>;
  1004.  
  1005.   rx-internal-delay-ps = <1500>;
  1006.   tx-internal-delay-ps = <1500>;
  1007.  
  1008.   phy-mode = "rgmii-id";
  1009.   phy-supply = <&vcc_io>;
  1010.   pinctrl-0 = <&rgmiim1_pins>;
  1011.   pinctrl-names = "default";
  1012.   snps,aal;
  1013.  
  1014.   phy-handle = <&yt8531c>;
  1015.   tx_delay = <0x5>;
  1016.   rx_delay = <0x0>;
  1017.   status = "okay";
  1018.  
  1019.   mdio {
  1020.    compatible = "snps,dwmac-mdio";
  1021.    #address-cells = <1>;
  1022.    #size-cells = <0>;
  1023.  
  1024.    yt8531c: ethernet-phy@0 {
  1025.     compatible = "ethernet-phy-ieee802.3-c22";
  1026.     reg = <1>;
  1027.  
  1028.     #rx-internal-delay-ps = <1500>;
  1029.     #tx-internal-delay-ps = <1500>;
  1030.  
  1031.     motorcomm,auto-sleep-disabled;
  1032.     motorcomm,clk-out-frequency-hz = <125000000>;
  1033.     motorcomm,keep-pll-enabled;
  1034.     motorcomm,rx-clk-drv-microamp = <5020>;
  1035.     motorcomm,rx-data-drv-microamp = <5020>;
  1036.  
  1037.     pinctrl-0 = <&eth_phy_reset_pin>;
  1038.     pinctrl-names = "default";
  1039.     reset-assert-us = <15000>;
  1040.     reset-deassert-us = <50000>;
  1041.     reset-gpios = <&gpio1 18 1>;
  1042.    };
  1043.   };
  1044.  };
  1045.  
  1046.  
  1047.  
  1048.  gmac2phy: ethernet@ff550000 {
  1049.   compatible = "rockchip,rk3328-gmac";
  1050.   reg = <0x0 0xff550000 0x0 0x10000>;
  1051.   rockchip,grf = <&grf>;
  1052.   interrupts = <0 21 4>;
  1053.   interrupt-names = "macirq";
  1054.   clocks = <&cru 84>, <&cru 83>,
  1055.     <&cru 83>, <&cru 85>,
  1056.     <&cru 149>, <&cru 222>,
  1057.     <&cru 86>;
  1058.   clock-names = "stmmaceth", "mac_clk_rx",
  1059.          "mac_clk_tx", "clk_mac_ref",
  1060.          "aclk_mac", "pclk_mac",
  1061.          "clk_macphy";
  1062.   resets = <&cru 98>;
  1063.   reset-names = "stmmaceth";
  1064.   phy-mode = "rgmii-id";
  1065.   phy-handle = <&phy>;
  1066.  
  1067.   rx-fifo-depth = <16384>;
  1068.   tx-fifo-depth = <8192>;
  1069.   rx-fifo-size = <4096>;
  1070.   tx-fifo-size = <4096>;
  1071.   rx-fifo-size-gige = <16384>;
  1072.   tx-fifo-size-gige = <8192>;
  1073.  
  1074.   snps,txpbl = <0x4>;
  1075.   clock_in_out = "output";
  1076.   status = "disabled";
  1077.  
  1078.   mdio {
  1079.    compatible = "snps,dwmac-mdio";
  1080.    #address-cells = <1>;
  1081.    #size-cells = <0>;
  1082.  
  1083.    phy: ethernet-phy@0 {
  1084.     compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
  1085.     reg = <0>;
  1086.     clocks = <&cru 86>;
  1087.     resets = <&cru 100>;
  1088.     pinctrl-names = "default";
  1089.     pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
  1090.     phy-is-integrated;
  1091.    };
  1092.   };
  1093.  };
  1094.  
  1095.  usb20_otg: usb@ff580000 {
  1096.   compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
  1097.         "snps,dwc2";
  1098.   reg = <0x0 0xff580000 0x0 0x40000>;
  1099.   interrupts = <0 23 4>;
  1100.   clocks = <&cru 333>;
  1101.   clock-names = "otg";
  1102.   dr_mode = "otg";
  1103.   g-np-tx-fifo-size = <16>;
  1104.   g-rx-fifo-size = <280>;
  1105.   g-tx-fifo-size = <256 128 128 64 32 16>;
  1106.   phys = <&u2phy_otg>;
  1107.   phy-names = "usb2-phy";
  1108.   status = "disabled";
  1109.  };
  1110.  
  1111.  usb_host0_ehci: usb@ff5c0000 {
  1112.   compatible = "generic-ehci";
  1113.   reg = <0x0 0xff5c0000 0x0 0x10000>;
  1114.   interrupts = <0 16 4>;
  1115.   clocks = <&cru 334>, <&u2phy>;
  1116.   phys = <&u2phy_host>;
  1117.   phy-names = "usb";
  1118.   status = "disabled";
  1119.  };
  1120.  
  1121.  usb_host0_ohci: usb@ff5d0000 {
  1122.   compatible = "generic-ohci";
  1123.   reg = <0x0 0xff5d0000 0x0 0x10000>;
  1124.   interrupts = <0 17 4>;
  1125.   clocks = <&cru 334>, <&u2phy>;
  1126.   phys = <&u2phy_host>;
  1127.   phy-names = "usb";
  1128.   status = "disabled";
  1129.  };
  1130.  
  1131.  sdmmc_ext: mmc@ff5f0000 {
  1132.   compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
  1133.   reg = <0x0 0xff5f0000 0x0 0x4000>;
  1134.   interrupts = <0 4 4>;
  1135.   clocks = <&cru 320>, <&cru 31>,
  1136.     <&cru 77>, <&cru 81>;
  1137.   clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  1138.   fifo-depth = <0x100>;
  1139.   max-frequency = <150000000>;
  1140.   resets = <&cru 104>;
  1141.   reset-names = "reset";
  1142.   status = "disabled";
  1143.  };
  1144.  
  1145.  usbdrd3: usb@ff600000 {
  1146.   compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
  1147.   reg = <0x0 0xff600000 0x0 0x100000>;
  1148.   interrupts = <0 67 4>;
  1149.   clocks = <&cru 96>, <&cru 97>,
  1150.     <&cru 132>;
  1151.   clock-names = "ref_clk", "suspend_clk",
  1152.          "bus_clk";
  1153.   dr_mode = "otg";
  1154.   phy_type = "utmi_wide";
  1155.   snps,dis-del-phy-power-chg-quirk;
  1156.   snps,dis_enblslpm_quirk;
  1157.   snps,dis-tx-ipgap-linecheck-quirk;
  1158.   snps,dis-u2-freeclk-exists-quirk;
  1159.   snps,dis_u2_susphy_quirk;
  1160.   snps,dis_u3_susphy_quirk;
  1161.   status = "disabled";
  1162.  };
  1163.  
  1164.  gic: interrupt-controller@ff811000 {
  1165.   compatible = "arm,gic-400";
  1166.   #interrupt-cells = <3>;
  1167.   #address-cells = <0>;
  1168.   interrupt-controller;
  1169.   reg = <0x0 0xff811000 0 0x1000>,
  1170.         <0x0 0xff812000 0 0x2000>,
  1171.         <0x0 0xff814000 0 0x2000>,
  1172.         <0x0 0xff816000 0 0x2000>;
  1173.   interrupts = <1 9
  1174.         ((((1 << (4)) - 1) << 8) | 4)>;
  1175.  };
  1176.  
  1177.  crypto: crypto@ff060000 {
  1178.   compatible = "rockchip,rk3328-crypto";
  1179.   reg = <0x0 0xff060000 0x0 0x4000>;
  1180.   interrupts = <0 30 4>;
  1181.   clocks = <&cru 336>, <&cru 337>,
  1182.     <&cru 59>;
  1183.   clock-names = "hclk_master", "hclk_slave", "sclk";
  1184.   resets = <&cru 68>;
  1185.   reset-names = "crypto-rst";
  1186.  };
  1187.  
  1188.  pinctrl: pinctrl {
  1189.   compatible = "rockchip,rk3328-pinctrl";
  1190.   rockchip,grf = <&grf>;
  1191.   #address-cells = <2>;
  1192.   #size-cells = <2>;
  1193.   ranges;
  1194.  
  1195.   gpio0: gpio@ff210000 {
  1196.    compatible = "rockchip,gpio-bank";
  1197.    reg = <0x0 0xff210000 0x0 0x100>;
  1198.    interrupts = <0 51 4>;
  1199.    clocks = <&cru 200>;
  1200.  
  1201.    gpio-controller;
  1202.    #gpio-cells = <2>;
  1203.  
  1204.    interrupt-controller;
  1205.    #interrupt-cells = <2>;
  1206.   };
  1207.  
  1208.   gpio1: gpio@ff220000 {
  1209.    compatible = "rockchip,gpio-bank";
  1210.    reg = <0x0 0xff220000 0x0 0x100>;
  1211.    interrupts = <0 52 4>;
  1212.    clocks = <&cru 201>;
  1213.  
  1214.    gpio-controller;
  1215.    #gpio-cells = <2>;
  1216.  
  1217.    interrupt-controller;
  1218.    #interrupt-cells = <2>;
  1219.   };
  1220.  
  1221.   gpio2: gpio@ff230000 {
  1222.    compatible = "rockchip,gpio-bank";
  1223.    reg = <0x0 0xff230000 0x0 0x100>;
  1224.    interrupts = <0 53 4>;
  1225.    clocks = <&cru 202>;
  1226.  
  1227.    gpio-controller;
  1228.    #gpio-cells = <2>;
  1229.  
  1230.    interrupt-controller;
  1231.    #interrupt-cells = <2>;
  1232.   };
  1233.  
  1234.   gpio3: gpio@ff240000 {
  1235.    compatible = "rockchip,gpio-bank";
  1236.    reg = <0x0 0xff240000 0x0 0x100>;
  1237.    interrupts = <0 54 4>;
  1238.    clocks = <&cru 203>;
  1239.  
  1240.    gpio-controller;
  1241.    #gpio-cells = <2>;
  1242.  
  1243.    interrupt-controller;
  1244.    #interrupt-cells = <2>;
  1245.   };
  1246.  
  1247.   pcfg_pull_up: pcfg-pull-up {
  1248.    bias-pull-up;
  1249.   };
  1250.  
  1251.   pcfg_pull_down: pcfg-pull-down {
  1252.    bias-pull-down;
  1253.   };
  1254.  
  1255.   pcfg_pull_none: pcfg-pull-none {
  1256.    bias-disable;
  1257.   };
  1258.  
  1259.   pcfg_pull_none_2ma: pcfg-pull-none-2ma {
  1260.    bias-disable;
  1261.    drive-strength = <2>;
  1262.   };
  1263.  
  1264.   pcfg_pull_up_2ma: pcfg-pull-up-2ma {
  1265.    bias-pull-up;
  1266.    drive-strength = <2>;
  1267.   };
  1268.  
  1269.   pcfg_pull_up_4ma: pcfg-pull-up-4ma {
  1270.    bias-pull-up;
  1271.    drive-strength = <4>;
  1272.   };
  1273.  
  1274.   pcfg_pull_none_4ma: pcfg-pull-none-4ma {
  1275.    bias-disable;
  1276.    drive-strength = <4>;
  1277.   };
  1278.  
  1279.   pcfg_pull_down_4ma: pcfg-pull-down-4ma {
  1280.    bias-pull-down;
  1281.    drive-strength = <4>;
  1282.   };
  1283.  
  1284.   pcfg_pull_none_8ma: pcfg-pull-none-8ma {
  1285.    bias-disable;
  1286.    drive-strength = <8>;
  1287.   };
  1288.  
  1289.   pcfg_pull_up_8ma: pcfg-pull-up-8ma {
  1290.    bias-pull-up;
  1291.    drive-strength = <8>;
  1292.   };
  1293.  
  1294.   pcfg_pull_none_12ma: pcfg-pull-none-12ma {
  1295.    bias-disable;
  1296.    drive-strength = <12>;
  1297.   };
  1298.  
  1299.   pcfg_pull_up_12ma: pcfg-pull-up-12ma {
  1300.    bias-pull-up;
  1301.    drive-strength = <12>;
  1302.   };
  1303.  
  1304.   pcfg_output_high: pcfg-output-high {
  1305.    output-high;
  1306.   };
  1307.  
  1308.   pcfg_output_low: pcfg-output-low {
  1309.    output-low;
  1310.   };
  1311.  
  1312.   pcfg_input_high: pcfg-input-high {
  1313.    bias-pull-up;
  1314.    input-enable;
  1315.   };
  1316.  
  1317.   pcfg_input: pcfg-input {
  1318.    input-enable;
  1319.   };
  1320.  
  1321.   i2c0 {
  1322.    i2c0_xfer: i2c0-xfer {
  1323.     rockchip,pins = <2 24 1 &pcfg_pull_none>,
  1324.       <2 25 1 &pcfg_pull_none>;
  1325.    };
  1326.   };
  1327.  
  1328.   i2c1 {
  1329.    i2c1_xfer: i2c1-xfer {
  1330.     rockchip,pins = <2 4 2 &pcfg_pull_none>,
  1331.       <2 5 2 &pcfg_pull_none>;
  1332.    };
  1333.   };
  1334.  
  1335.   i2c2 {
  1336.    i2c2_xfer: i2c2-xfer {
  1337.     rockchip,pins = <2 13 1 &pcfg_pull_none>,
  1338.       <2 14 1 &pcfg_pull_none>;
  1339.    };
  1340.   };
  1341.  
  1342.   i2c3 {
  1343.    i2c3_xfer: i2c3-xfer {
  1344.     rockchip,pins = <0 5 2 &pcfg_pull_none>,
  1345.       <0 6 2 &pcfg_pull_none>;
  1346.    };
  1347.    i2c3_pins: i2c3-pins {
  1348.     rockchip,pins =
  1349.      <0 5 0 &pcfg_pull_none>,
  1350.      <0 6 0 &pcfg_pull_none>;
  1351.    };
  1352.   };
  1353.  
  1354.   hdmi_i2c {
  1355.    hdmii2c_xfer: hdmii2c-xfer {
  1356.     rockchip,pins = <0 5 1 &pcfg_pull_none>,
  1357.       <0 6 1 &pcfg_pull_none>;
  1358.    };
  1359.   };
  1360.  
  1361.   pdm-0 {
  1362.    pdmm0_clk: pdmm0-clk {
  1363.     rockchip,pins = <2 18 2 &pcfg_pull_none>;
  1364.    };
  1365.  
  1366.    pdmm0_fsync: pdmm0-fsync {
  1367.     rockchip,pins = <2 23 2 &pcfg_pull_none>;
  1368.    };
  1369.  
  1370.    pdmm0_sdi0: pdmm0-sdi0 {
  1371.     rockchip,pins = <2 19 2 &pcfg_pull_none>;
  1372.    };
  1373.  
  1374.    pdmm0_sdi1: pdmm0-sdi1 {
  1375.     rockchip,pins = <2 20 2 &pcfg_pull_none>;
  1376.    };
  1377.  
  1378.    pdmm0_sdi2: pdmm0-sdi2 {
  1379.     rockchip,pins = <2 21 2 &pcfg_pull_none>;
  1380.    };
  1381.  
  1382.    pdmm0_sdi3: pdmm0-sdi3 {
  1383.     rockchip,pins = <2 22 2 &pcfg_pull_none>;
  1384.    };
  1385.  
  1386.    pdmm0_clk_sleep: pdmm0-clk-sleep {
  1387.     rockchip,pins =
  1388.      <2 18 0 &pcfg_input_high>;
  1389.    };
  1390.  
  1391.    pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
  1392.     rockchip,pins =
  1393.      <2 19 0 &pcfg_input_high>;
  1394.    };
  1395.  
  1396.    pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
  1397.     rockchip,pins =
  1398.      <2 20 0 &pcfg_input_high>;
  1399.    };
  1400.  
  1401.    pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
  1402.     rockchip,pins =
  1403.      <2 21 0 &pcfg_input_high>;
  1404.    };
  1405.  
  1406.    pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
  1407.     rockchip,pins =
  1408.      <2 22 0 &pcfg_input_high>;
  1409.    };
  1410.  
  1411.    pdmm0_fsync_sleep: pdmm0-fsync-sleep {
  1412.     rockchip,pins =
  1413.      <2 23 0 &pcfg_input_high>;
  1414.    };
  1415.   };
  1416.  
  1417.   tsadc {
  1418.    otp_pin: otp-pin {
  1419.     rockchip,pins = <2 13 0 &pcfg_pull_none>;
  1420.    };
  1421.  
  1422.    otp_out: otp-out {
  1423.     rockchip,pins = <2 13 1 &pcfg_pull_none>;
  1424.    };
  1425.   };
  1426.  
  1427.   uart0 {
  1428.    uart0_xfer: uart0-xfer {
  1429.     rockchip,pins = <1 9 1 &pcfg_pull_none>,
  1430.       <1 8 1 &pcfg_pull_up>;
  1431.    };
  1432.  
  1433.    uart0_cts: uart0-cts {
  1434.     rockchip,pins = <1 11 1 &pcfg_pull_none>;
  1435.    };
  1436.  
  1437.    uart0_rts: uart0-rts {
  1438.     rockchip,pins = <1 10 1 &pcfg_pull_none>;
  1439.    };
  1440.  
  1441.    uart0_rts_pin: uart0-rts-pin {
  1442.     rockchip,pins = <1 10 0 &pcfg_pull_none>;
  1443.    };
  1444.   };
  1445.  
  1446.   uart1 {
  1447.    uart1_xfer: uart1-xfer {
  1448.     rockchip,pins = <3 4 4 &pcfg_pull_none>,
  1449.       <3 6 4 &pcfg_pull_up>;
  1450.    };
  1451.  
  1452.    uart1_cts: uart1-cts {
  1453.     rockchip,pins = <3 7 4 &pcfg_pull_none>;
  1454.    };
  1455.  
  1456.    uart1_rts: uart1-rts {
  1457.     rockchip,pins = <3 5 4 &pcfg_pull_none>;
  1458.    };
  1459.  
  1460.    uart1_rts_pin: uart1-rts-pin {
  1461.     rockchip,pins = <3 5 0 &pcfg_pull_none>;
  1462.    };
  1463.   };
  1464.  
  1465.   uart2-0 {
  1466.    uart2m0_xfer: uart2m0-xfer {
  1467.     rockchip,pins = <1 0 2 &pcfg_pull_none>,
  1468.       <1 1 2 &pcfg_pull_up>;
  1469.    };
  1470.   };
  1471.  
  1472.   uart2-1 {
  1473.    uart2m1_xfer: uart2m1-xfer {
  1474.     rockchip,pins = <2 0 1 &pcfg_pull_none>,
  1475.       <2 1 1 &pcfg_pull_up>;
  1476.    };
  1477.   };
  1478.  
  1479.   spi0-0 {
  1480.    spi0m0_clk: spi0m0-clk {
  1481.     rockchip,pins = <2 8 1 &pcfg_pull_up>;
  1482.    };
  1483.  
  1484.    spi0m0_cs0: spi0m0-cs0 {
  1485.     rockchip,pins = <2 11 1 &pcfg_pull_up>;
  1486.    };
  1487.  
  1488.    spi0m0_tx: spi0m0-tx {
  1489.     rockchip,pins = <2 9 1 &pcfg_pull_up>;
  1490.    };
  1491.  
  1492.    spi0m0_rx: spi0m0-rx {
  1493.     rockchip,pins = <2 10 1 &pcfg_pull_up>;
  1494.    };
  1495.  
  1496.    spi0m0_cs1: spi0m0-cs1 {
  1497.     rockchip,pins = <2 12 1 &pcfg_pull_up>;
  1498.    };
  1499.   };
  1500.  
  1501.   spi0-1 {
  1502.    spi0m1_clk: spi0m1-clk {
  1503.     rockchip,pins = <3 23 2 &pcfg_pull_up>;
  1504.    };
  1505.  
  1506.    spi0m1_cs0: spi0m1-cs0 {
  1507.     rockchip,pins = <3 26 2 &pcfg_pull_up>;
  1508.    };
  1509.  
  1510.    spi0m1_tx: spi0m1-tx {
  1511.     rockchip,pins = <3 25 2 &pcfg_pull_up>;
  1512.    };
  1513.  
  1514.    spi0m1_rx: spi0m1-rx {
  1515.     rockchip,pins = <3 24 2 &pcfg_pull_up>;
  1516.    };
  1517.  
  1518.    spi0m1_cs1: spi0m1-cs1 {
  1519.     rockchip,pins = <3 27 2 &pcfg_pull_up>;
  1520.    };
  1521.   };
  1522.  
  1523.   spi0-2 {
  1524.    spi0m2_clk: spi0m2-clk {
  1525.     rockchip,pins = <3 0 4 &pcfg_pull_up>;
  1526.    };
  1527.  
  1528.    spi0m2_cs0: spi0m2-cs0 {
  1529.     rockchip,pins = <3 8 3 &pcfg_pull_up>;
  1530.    };
  1531.  
  1532.    spi0m2_tx: spi0m2-tx {
  1533.     rockchip,pins = <3 1 4 &pcfg_pull_up>;
  1534.    };
  1535.  
  1536.    spi0m2_rx: spi0m2-rx {
  1537.     rockchip,pins = <3 2 4 &pcfg_pull_up>;
  1538.    };
  1539.   };
  1540.  
  1541.   i2s1 {
  1542.    i2s1_mclk: i2s1-mclk {
  1543.     rockchip,pins = <2 15 1 &pcfg_pull_none>;
  1544.    };
  1545.  
  1546.    i2s1_sclk: i2s1-sclk {
  1547.     rockchip,pins = <2 18 1 &pcfg_pull_none>;
  1548.    };
  1549.  
  1550.    i2s1_lrckrx: i2s1-lrckrx {
  1551.     rockchip,pins = <2 16 1 &pcfg_pull_none>;
  1552.    };
  1553.  
  1554.    i2s1_lrcktx: i2s1-lrcktx {
  1555.     rockchip,pins = <2 17 1 &pcfg_pull_none>;
  1556.    };
  1557.  
  1558.    i2s1_sdi: i2s1-sdi {
  1559.     rockchip,pins = <2 19 1 &pcfg_pull_none>;
  1560.    };
  1561.  
  1562.    i2s1_sdo: i2s1-sdo {
  1563.     rockchip,pins = <2 23 1 &pcfg_pull_none>;
  1564.    };
  1565.  
  1566.    i2s1_sdio1: i2s1-sdio1 {
  1567.     rockchip,pins = <2 20 1 &pcfg_pull_none>;
  1568.    };
  1569.  
  1570.    i2s1_sdio2: i2s1-sdio2 {
  1571.     rockchip,pins = <2 21 1 &pcfg_pull_none>;
  1572.    };
  1573.  
  1574.    i2s1_sdio3: i2s1-sdio3 {
  1575.     rockchip,pins = <2 22 1 &pcfg_pull_none>;
  1576.    };
  1577.  
  1578.    i2s1_sleep: i2s1-sleep {
  1579.     rockchip,pins =
  1580.      <2 15 0 &pcfg_input_high>,
  1581.      <2 16 0 &pcfg_input_high>,
  1582.      <2 17 0 &pcfg_input_high>,
  1583.      <2 18 0 &pcfg_input_high>,
  1584.      <2 19 0 &pcfg_input_high>,
  1585.      <2 20 0 &pcfg_input_high>,
  1586.      <2 21 0 &pcfg_input_high>,
  1587.      <2 22 0 &pcfg_input_high>,
  1588.      <2 23 0 &pcfg_input_high>;
  1589.    };
  1590.   };
  1591.  
  1592.   i2s2-0 {
  1593.    i2s2m0_mclk: i2s2m0-mclk {
  1594.     rockchip,pins = <1 21 1 &pcfg_pull_none>;
  1595.    };
  1596.  
  1597.    i2s2m0_sclk: i2s2m0-sclk {
  1598.     rockchip,pins = <1 22 1 &pcfg_pull_none>;
  1599.    };
  1600.  
  1601.    i2s2m0_lrckrx: i2s2m0-lrckrx {
  1602.     rockchip,pins = <1 26 1 &pcfg_pull_none>;
  1603.    };
  1604.  
  1605.    i2s2m0_lrcktx: i2s2m0-lrcktx {
  1606.     rockchip,pins = <1 23 1 &pcfg_pull_none>;
  1607.    };
  1608.  
  1609.    i2s2m0_sdi: i2s2m0-sdi {
  1610.     rockchip,pins = <1 24 1 &pcfg_pull_none>;
  1611.    };
  1612.  
  1613.    i2s2m0_sdo: i2s2m0-sdo {
  1614.     rockchip,pins = <1 25 1 &pcfg_pull_none>;
  1615.    };
  1616.  
  1617.    i2s2m0_sleep: i2s2m0-sleep {
  1618.     rockchip,pins =
  1619.      <1 21 0 &pcfg_input_high>,
  1620.      <1 22 0 &pcfg_input_high>,
  1621.      <1 26 0 &pcfg_input_high>,
  1622.      <1 23 0 &pcfg_input_high>,
  1623.      <1 24 0 &pcfg_input_high>,
  1624.      <1 25 0 &pcfg_input_high>;
  1625.    };
  1626.   };
  1627.  
  1628.   i2s2-1 {
  1629.    i2s2m1_mclk: i2s2m1-mclk {
  1630.     rockchip,pins = <1 21 1 &pcfg_pull_none>;
  1631.    };
  1632.  
  1633.    i2s2m1_sclk: i2s2m1-sclk {
  1634.     rockchip,pins = <3 0 6 &pcfg_pull_none>;
  1635.    };
  1636.  
  1637.    i2s2m1_lrckrx: i2sm1-lrckrx {
  1638.     rockchip,pins = <3 8 6 &pcfg_pull_none>;
  1639.    };
  1640.  
  1641.    i2s2m1_lrcktx: i2s2m1-lrcktx {
  1642.     rockchip,pins = <3 8 4 &pcfg_pull_none>;
  1643.    };
  1644.  
  1645.    i2s2m1_sdi: i2s2m1-sdi {
  1646.     rockchip,pins = <3 2 6 &pcfg_pull_none>;
  1647.    };
  1648.  
  1649.    i2s2m1_sdo: i2s2m1-sdo {
  1650.     rockchip,pins = <3 1 6 &pcfg_pull_none>;
  1651.    };
  1652.  
  1653.    i2s2m1_sleep: i2s2m1-sleep {
  1654.     rockchip,pins =
  1655.      <1 21 0 &pcfg_input_high>,
  1656.      <3 0 0 &pcfg_input_high>,
  1657.      <3 8 0 &pcfg_input_high>,
  1658.      <3 2 0 &pcfg_input_high>,
  1659.      <3 1 0 &pcfg_input_high>;
  1660.    };
  1661.   };
  1662.  
  1663.   spdif-0 {
  1664.    spdifm0_tx: spdifm0-tx {
  1665.     rockchip,pins = <0 27 1 &pcfg_pull_none>;
  1666.    };
  1667.   };
  1668.  
  1669.   spdif-1 {
  1670.    spdifm1_tx: spdifm1-tx {
  1671.     rockchip,pins = <2 17 2 &pcfg_pull_none>;
  1672.    };
  1673.   };
  1674.  
  1675.   spdif-2 {
  1676.    spdifm2_tx: spdifm2-tx {
  1677.     rockchip,pins = <0 2 2 &pcfg_pull_none>;
  1678.    };
  1679.   };
  1680.  
  1681.   sdmmc0-0 {
  1682.    sdmmc0m0_pwren: sdmmc0m0-pwren {
  1683.     rockchip,pins = <2 7 1 &pcfg_pull_up_4ma>;
  1684.    };
  1685.  
  1686.    sdmmc0m0_pin: sdmmc0m0-pin {
  1687.     rockchip,pins = <2 7 0 &pcfg_pull_up_4ma>;
  1688.    };
  1689.   };
  1690.  
  1691.   sdmmc0-1 {
  1692.    sdmmc0m1_pwren: sdmmc0m1-pwren {
  1693.     rockchip,pins = <0 30 3 &pcfg_pull_up_4ma>;
  1694.    };
  1695.  
  1696.    sdmmc0m1_pin: sdmmc0m1-pin {
  1697.     rockchip,pins = <0 30 0 &pcfg_pull_up_4ma>;
  1698.    };
  1699.   };
  1700.  
  1701.   sdmmc0 {
  1702.    sdmmc0_clk: sdmmc0-clk {
  1703.     rockchip,pins = <1 6 1 &pcfg_pull_none_8ma>;
  1704.    };
  1705.  
  1706.    sdmmc0_cmd: sdmmc0-cmd {
  1707.     rockchip,pins = <1 4 1 &pcfg_pull_up_8ma>;
  1708.    };
  1709.  
  1710.    sdmmc0_dectn: sdmmc0-dectn {
  1711.     rockchip,pins = <1 5 1 &pcfg_pull_up_4ma>;
  1712.    };
  1713.  
  1714.    sdmmc0_wrprt: sdmmc0-wrprt {
  1715.     rockchip,pins = <1 7 1 &pcfg_pull_up_4ma>;
  1716.    };
  1717.  
  1718.    sdmmc0_bus1: sdmmc0-bus1 {
  1719.     rockchip,pins = <1 0 1 &pcfg_pull_up_8ma>;
  1720.    };
  1721.  
  1722.    sdmmc0_bus4: sdmmc0-bus4 {
  1723.     rockchip,pins = <1 0 1 &pcfg_pull_up_8ma>,
  1724.       <1 1 1 &pcfg_pull_up_8ma>,
  1725.       <1 2 1 &pcfg_pull_up_8ma>,
  1726.       <1 3 1 &pcfg_pull_up_8ma>;
  1727.    };
  1728.  
  1729.    sdmmc0_pins: sdmmc0-pins {
  1730.     rockchip,pins =
  1731.      <1 6 0 &pcfg_pull_up_4ma>,
  1732.      <1 4 0 &pcfg_pull_up_4ma>,
  1733.      <1 5 0 &pcfg_pull_up_4ma>,
  1734.      <1 7 0 &pcfg_pull_up_4ma>,
  1735.      <1 3 0 &pcfg_pull_up_4ma>,
  1736.      <1 2 0 &pcfg_pull_up_4ma>,
  1737.      <1 1 0 &pcfg_pull_up_4ma>,
  1738.      <1 0 0 &pcfg_pull_up_4ma>;
  1739.    };
  1740.   };
  1741.  
  1742.   sdmmc0ext {
  1743.    sdmmc0ext_clk: sdmmc0ext-clk {
  1744.     rockchip,pins = <3 2 3 &pcfg_pull_none_4ma>;
  1745.    };
  1746.  
  1747.    sdmmc0ext_cmd: sdmmc0ext-cmd {
  1748.     rockchip,pins = <3 0 3 &pcfg_pull_up_4ma>;
  1749.    };
  1750.  
  1751.    sdmmc0ext_wrprt: sdmmc0ext-wrprt {
  1752.     rockchip,pins = <3 3 3 &pcfg_pull_up_4ma>;
  1753.    };
  1754.  
  1755.    sdmmc0ext_dectn: sdmmc0ext-dectn {
  1756.     rockchip,pins = <3 1 3 &pcfg_pull_up_4ma>;
  1757.    };
  1758.  
  1759.    sdmmc0ext_bus1: sdmmc0ext-bus1 {
  1760.     rockchip,pins = <3 4 3 &pcfg_pull_up_4ma>;
  1761.    };
  1762.  
  1763.    sdmmc0ext_bus4: sdmmc0ext-bus4 {
  1764.     rockchip,pins =
  1765.      <3 4 3 &pcfg_pull_up_4ma>,
  1766.      <3 5 3 &pcfg_pull_up_4ma>,
  1767.      <3 6 3 &pcfg_pull_up_4ma>,
  1768.      <3 7 3 &pcfg_pull_up_4ma>;
  1769.    };
  1770.  
  1771.    sdmmc0ext_pins: sdmmc0ext-pins {
  1772.     rockchip,pins =
  1773.      <3 0 0 &pcfg_pull_up_4ma>,
  1774.      <3 1 0 &pcfg_pull_up_4ma>,
  1775.      <3 2 0 &pcfg_pull_up_4ma>,
  1776.      <3 3 0 &pcfg_pull_up_4ma>,
  1777.      <3 4 0 &pcfg_pull_up_4ma>,
  1778.      <3 5 0 &pcfg_pull_up_4ma>,
  1779.      <3 6 0 &pcfg_pull_up_4ma>,
  1780.      <3 7 0 &pcfg_pull_up_4ma>;
  1781.    };
  1782.   };
  1783.  
  1784.   sdmmc1 {
  1785.    sdmmc1_clk: sdmmc1-clk {
  1786.     rockchip,pins = <1 12 1 &pcfg_pull_none_8ma>;
  1787.    };
  1788.  
  1789.    sdmmc1_cmd: sdmmc1-cmd {
  1790.     rockchip,pins = <1 13 1 &pcfg_pull_up_8ma>;
  1791.    };
  1792.  
  1793.    sdmmc1_pwren: sdmmc1-pwren {
  1794.     rockchip,pins = <1 18 1 &pcfg_pull_up_8ma>;
  1795.    };
  1796.  
  1797.    sdmmc1_wrprt: sdmmc1-wrprt {
  1798.     rockchip,pins = <1 20 1 &pcfg_pull_up_8ma>;
  1799.    };
  1800.  
  1801.    sdmmc1_dectn: sdmmc1-dectn {
  1802.     rockchip,pins = <1 19 1 &pcfg_pull_up_8ma>;
  1803.    };
  1804.  
  1805.    sdmmc1_bus1: sdmmc1-bus1 {
  1806.     rockchip,pins = <1 14 1 &pcfg_pull_up_8ma>;
  1807.    };
  1808.  
  1809.    sdmmc1_bus4: sdmmc1-bus4 {
  1810.     rockchip,pins = <1 14 1 &pcfg_pull_up_8ma>,
  1811.       <1 15 1 &pcfg_pull_up_8ma>,
  1812.       <1 16 1 &pcfg_pull_up_8ma>,
  1813.       <1 17 1 &pcfg_pull_up_8ma>;
  1814.    };
  1815.  
  1816.    sdmmc1_pins: sdmmc1-pins {
  1817.     rockchip,pins =
  1818.      <1 12 0 &pcfg_pull_up_4ma>,
  1819.      <1 13 0 &pcfg_pull_up_4ma>,
  1820.      <1 14 0 &pcfg_pull_up_4ma>,
  1821.      <1 15 0 &pcfg_pull_up_4ma>,
  1822.      <1 16 0 &pcfg_pull_up_4ma>,
  1823.      <1 17 0 &pcfg_pull_up_4ma>,
  1824.      <1 18 0 &pcfg_pull_up_4ma>,
  1825.      <1 19 0 &pcfg_pull_up_4ma>,
  1826.      <1 20 0 &pcfg_pull_up_4ma>;
  1827.    };
  1828.   };
  1829.  
  1830.   emmc {
  1831.    emmc_clk: emmc-clk {
  1832.     rockchip,pins = <3 21 2 &pcfg_pull_none_12ma>;
  1833.    };
  1834.  
  1835.    emmc_cmd: emmc-cmd {
  1836.     rockchip,pins = <3 19 2 &pcfg_pull_up_12ma>;
  1837.    };
  1838.  
  1839.    emmc_pwren: emmc-pwren {
  1840.     rockchip,pins = <3 22 2 &pcfg_pull_none>;
  1841.    };
  1842.  
  1843.    emmc_rstnout: emmc-rstnout {
  1844.     rockchip,pins = <3 20 2 &pcfg_pull_none>;
  1845.    };
  1846.  
  1847.    emmc_bus1: emmc-bus1 {
  1848.     rockchip,pins = <0 7 2 &pcfg_pull_up_12ma>;
  1849.    };
  1850.  
  1851.    emmc_bus4: emmc-bus4 {
  1852.     rockchip,pins =
  1853.      <0 7 2 &pcfg_pull_up_12ma>,
  1854.      <2 28 2 &pcfg_pull_up_12ma>,
  1855.      <2 29 2 &pcfg_pull_up_12ma>,
  1856.      <2 30 2 &pcfg_pull_up_12ma>;
  1857.    };
  1858.  
  1859.    emmc_bus8: emmc-bus8 {
  1860.     rockchip,pins =
  1861.      <0 7 2 &pcfg_pull_up_12ma>,
  1862.      <2 28 2 &pcfg_pull_up_12ma>,
  1863.      <2 29 2 &pcfg_pull_up_12ma>,
  1864.      <2 30 2 &pcfg_pull_up_12ma>,
  1865.      <2 31 2 &pcfg_pull_up_12ma>,
  1866.      <3 16 2 &pcfg_pull_up_12ma>,
  1867.      <3 17 2 &pcfg_pull_up_12ma>,
  1868.      <3 18 2 &pcfg_pull_up_12ma>;
  1869.    };
  1870.   };
  1871.  
  1872.   pwm0 {
  1873.    pwm0_pin: pwm0-pin {
  1874.     rockchip,pins = <2 4 1 &pcfg_pull_none>;
  1875.    };
  1876.   };
  1877.  
  1878.   pwm1 {
  1879.    pwm1_pin: pwm1-pin {
  1880.     rockchip,pins = <2 5 1 &pcfg_pull_none>;
  1881.    };
  1882.   };
  1883.  
  1884.   pwm2 {
  1885.    pwm2_pin: pwm2-pin {
  1886.     rockchip,pins = <2 6 1 &pcfg_pull_none>;
  1887.    };
  1888.   };
  1889.  
  1890.   pwmir {
  1891.    pwmir_pin: pwmir-pin {
  1892.     rockchip,pins = <2 2 1 &pcfg_pull_none>;
  1893.    };
  1894.   };
  1895.  
  1896.   gmac-1 {
  1897.    rgmiim1_pins: rgmiim1-pins {
  1898.     rockchip,pins =
  1899.  
  1900.      <1 12 2 &pcfg_pull_none_8ma>,
  1901.  
  1902.      <1 13 2 &pcfg_pull_none_4ma>,
  1903.  
  1904.      <1 19 2 &pcfg_pull_none_4ma>,
  1905.  
  1906.      <1 25 2 &pcfg_pull_none_8ma>,
  1907.  
  1908.      <1 21 2 &pcfg_pull_none_4ma>,
  1909.  
  1910.      <1 22 2 &pcfg_pull_none_4ma>,
  1911.  
  1912.      <1 23 2 &pcfg_pull_none_4ma>,
  1913.  
  1914.      <1 10 2 &pcfg_pull_none_4ma>,
  1915.  
  1916.      <1 11 2 &pcfg_pull_none_4ma>,
  1917.  
  1918.      <1 8 2 &pcfg_pull_none_8ma>,
  1919.  
  1920.      <1 9 2 &pcfg_pull_none_8ma>,
  1921.  
  1922.      <1 14 2 &pcfg_pull_none_4ma>,
  1923.  
  1924.      <1 15 2 &pcfg_pull_none_4ma>,
  1925.  
  1926.      <1 16 2 &pcfg_pull_none_8ma>,
  1927.  
  1928.      <1 17 2 &pcfg_pull_none_8ma>,
  1929.  
  1930.  
  1931.      <0 8 1 &pcfg_pull_none_8ma>,
  1932.  
  1933.      <0 12 1 &pcfg_pull_none_8ma>,
  1934.  
  1935.      <0 24 1 &pcfg_pull_none_4ma>,
  1936.  
  1937.      <0 16 1 &pcfg_pull_none_8ma>,
  1938.  
  1939.      <0 17 1 &pcfg_pull_none_8ma>,
  1940.  
  1941.      <0 23 1 &pcfg_pull_none_8ma>,
  1942.  
  1943.      <0 22 1 &pcfg_pull_none_8ma>;
  1944.    };
  1945.  
  1946.    rmiim1_pins: rmiim1-pins {
  1947.     rockchip,pins =
  1948.  
  1949.      <1 19 2 &pcfg_pull_none_2ma>,
  1950.  
  1951.      <1 25 2 &pcfg_pull_none_12ma>,
  1952.  
  1953.      <1 21 2 &pcfg_pull_none_2ma>,
  1954.  
  1955.      <1 24 2 &pcfg_pull_none_2ma>,
  1956.  
  1957.      <1 22 2 &pcfg_pull_none_2ma>,
  1958.  
  1959.      <1 23 2 &pcfg_pull_none_2ma>,
  1960.  
  1961.      <1 10 2 &pcfg_pull_none_2ma>,
  1962.  
  1963.      <1 11 2 &pcfg_pull_none_2ma>,
  1964.  
  1965.      <1 8 2 &pcfg_pull_none_12ma>,
  1966.  
  1967.      <1 9 2 &pcfg_pull_none_12ma>,
  1968.  
  1969.  
  1970.      <0 11 1 &pcfg_pull_none>,
  1971.  
  1972.      <0 12 1 &pcfg_pull_none>,
  1973.  
  1974.      <0 24 1 &pcfg_pull_none>,
  1975.  
  1976.      <0 19 1 &pcfg_pull_none>,
  1977.  
  1978.      <0 16 1 &pcfg_pull_none>,
  1979.  
  1980.      <0 17 1 &pcfg_pull_none>;
  1981.    };
  1982.   };
  1983.  
  1984.   gmac2phy {
  1985.    fephyled_speed10: fephyled-speed10 {
  1986.     rockchip,pins = <0 30 1 &pcfg_pull_none>;
  1987.    };
  1988.  
  1989.    fephyled_duplex: fephyled-duplex {
  1990.     rockchip,pins = <0 30 2 &pcfg_pull_none>;
  1991.    };
  1992.  
  1993.    fephyled_rxm1: fephyled-rxm1 {
  1994.     rockchip,pins = <2 25 2 &pcfg_pull_none>;
  1995.    };
  1996.  
  1997.    fephyled_txm1: fephyled-txm1 {
  1998.     rockchip,pins = <2 25 3 &pcfg_pull_none>;
  1999.    };
  2000.  
  2001.    fephyled_linkm1: fephyled-linkm1 {
  2002.     rockchip,pins = <2 24 2 &pcfg_pull_none>;
  2003.    };
  2004.   };
  2005.  
  2006.   tsadc_pin {
  2007.    tsadc_int: tsadc-int {
  2008.     rockchip,pins = <2 13 2 &pcfg_pull_none>;
  2009.    };
  2010.    tsadc_pin: tsadc-pin {
  2011.     rockchip,pins = <2 13 0 &pcfg_pull_none>;
  2012.    };
  2013.   };
  2014.  
  2015.   hdmi_pin {
  2016.    hdmi_cec: hdmi-cec {
  2017.     rockchip,pins = <0 3 1 &pcfg_pull_none>;
  2018.    };
  2019.  
  2020.    hdmi_hpd: hdmi-hpd {
  2021.     rockchip,pins = <0 4 1 &pcfg_pull_down>;
  2022.    };
  2023.   };
  2024.  
  2025.   cif-0 {
  2026.    dvp_d2d9_m0:dvp-d2d9-m0 {
  2027.     rockchip,pins =
  2028.  
  2029.      <3 4 2 &pcfg_pull_none>,
  2030.  
  2031.      <3 5 2 &pcfg_pull_none>,
  2032.  
  2033.      <3 6 2 &pcfg_pull_none>,
  2034.  
  2035.      <3 7 2 &pcfg_pull_none>,
  2036.  
  2037.      <3 8 2 &pcfg_pull_none>,
  2038.  
  2039.      <3 9 2 &pcfg_pull_none>,
  2040.  
  2041.      <3 10 2 &pcfg_pull_none>,
  2042.  
  2043.      <3 11 2 &pcfg_pull_none>,
  2044.  
  2045.      <3 1 2 &pcfg_pull_none>,
  2046.  
  2047.      <3 0 2 &pcfg_pull_none>,
  2048.  
  2049.      <3 3 2 &pcfg_pull_none>,
  2050.  
  2051.      <3 2 2 &pcfg_pull_none>;
  2052.    };
  2053.   };
  2054.  
  2055.   cif-1 {
  2056.    dvp_d2d9_m1:dvp-d2d9-m1 {
  2057.     rockchip,pins =
  2058.  
  2059.      <3 4 2 &pcfg_pull_none>,
  2060.  
  2061.      <3 5 2 &pcfg_pull_none>,
  2062.  
  2063.      <3 6 2 &pcfg_pull_none>,
  2064.  
  2065.      <3 7 2 &pcfg_pull_none>,
  2066.  
  2067.      <3 8 2 &pcfg_pull_none>,
  2068.  
  2069.      <2 16 4 &pcfg_pull_none>,
  2070.  
  2071.      <2 17 4 &pcfg_pull_none>,
  2072.  
  2073.      <2 18 4 &pcfg_pull_none>,
  2074.  
  2075.      <3 1 2 &pcfg_pull_none>,
  2076.  
  2077.      <3 0 2 &pcfg_pull_none>,
  2078.  
  2079.      <2 15 4 &pcfg_pull_none>,
  2080.  
  2081.      <3 2 2 &pcfg_pull_none>;
  2082.    };
  2083.   };
  2084.  };
  2085. };
  2086. # 12 "rk3328-orangepi-r1-plus.dtsi" 2
  2087.  
  2088. / {
  2089.  aliases {
  2090.   ethernet0 = &gmac2io;
  2091.   ethernet1 = &rtl8153;
  2092.   mmc0 = &sdmmc;
  2093.  };
  2094.  
  2095.  chosen {
  2096.   stdout-path = "serial2:1500000n8";
  2097.  };
  2098.  
  2099.  gmac_clk: gmac-clock {
  2100.   compatible = "fixed-clock";
  2101.   clock-frequency = <125000000>;
  2102.   clock-output-names = "gmac_clkin";
  2103.   #clock-cells = <0>;
  2104.  };
  2105.  
  2106.  leds {
  2107.   compatible = "gpio-leds";
  2108.   pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
  2109.   pinctrl-names = "default";
  2110.  
  2111.   led-0 {
  2112.    function = "lan";
  2113.    color = <2>;
  2114.    gpios = <&gpio2 15 0>;
  2115.   };
  2116.  
  2117.   led-1 {
  2118.    function = "status";
  2119.    color = <1>;
  2120.    gpios = <&gpio3 21 0>;
  2121.    linux,default-trigger = "heartbeat";
  2122.   };
  2123.  
  2124.   led-2 {
  2125.    function = "wan";
  2126.    color = <2>;
  2127.    gpios = <&gpio2 18 0>;
  2128.   };
  2129.  };
  2130.  
  2131.  vcc_sd: regulator-sdmmc {
  2132.   compatible = "regulator-fixed";
  2133.   gpio = <&gpio0 30 1>;
  2134.   pinctrl-0 = <&sdmmc0m1_pin>;
  2135.   pinctrl-names = "default";
  2136.   regulator-name = "vcc_sd";
  2137.   regulator-boot-on;
  2138.   vin-supply = <&vcc_io>;
  2139.  };
  2140.  
  2141.  vcc_sys: regulator-vcc-sys {
  2142.   compatible = "regulator-fixed";
  2143.   regulator-name = "vcc_sys";
  2144.   regulator-always-on;
  2145.   regulator-boot-on;
  2146.   regulator-min-microvolt = <5000000>;
  2147.   regulator-max-microvolt = <5000000>;
  2148.  };
  2149.  
  2150.  vdd_5v_lan: regulator-vdd-5v-lan {
  2151.   compatible = "regulator-fixed";
  2152.   enable-active-high;
  2153.   gpio = <&gpio2 22 0>;
  2154.   pinctrl-0 = <&lan_vdd_pin>;
  2155.   pinctrl-names = "default";
  2156.   regulator-name = "vdd_5v_lan";
  2157.   regulator-always-on;
  2158.   regulator-boot-on;
  2159.   vin-supply = <&vcc_sys>;
  2160.  };
  2161. };
  2162.  
  2163. &cpu0 {
  2164.  cpu-supply = <&vdd_arm>;
  2165. };
  2166.  
  2167. &cpu1 {
  2168.  cpu-supply = <&vdd_arm>;
  2169. };
  2170.  
  2171. &cpu2 {
  2172.  cpu-supply = <&vdd_arm>;
  2173. };
  2174.  
  2175. &cpu3 {
  2176.  cpu-supply = <&vdd_arm>;
  2177. };
  2178.  
  2179. &display_subsystem {
  2180.  status = "disabled";
  2181. };
  2182.  
  2183.  
  2184. &i2c1 {
  2185.  status = "okay";
  2186.  
  2187.  rk805: pmic@18 {
  2188.   compatible = "rockchip,rk805";
  2189.   reg = <0x18>;
  2190.   interrupt-parent = <&gpio1>;
  2191.   interrupts = <24 8>;
  2192.   #clock-cells = <1>;
  2193.   clock-output-names = "xin32k", "rk805-clkout2";
  2194.   gpio-controller;
  2195.   #gpio-cells = <2>;
  2196.   pinctrl-0 = <&pmic_int_l>;
  2197.   pinctrl-names = "default";
  2198.   system-power-controller;
  2199.   wakeup-source;
  2200.  
  2201.   vcc1-supply = <&vcc_sys>;
  2202.   vcc2-supply = <&vcc_sys>;
  2203.   vcc3-supply = <&vcc_sys>;
  2204.   vcc4-supply = <&vcc_sys>;
  2205.   vcc5-supply = <&vcc_io>;
  2206.   vcc6-supply = <&vcc_sys>;
  2207.  
  2208.   regulators {
  2209.    vdd_log: DCDC_REG1 {
  2210.     regulator-name = "vdd_log";
  2211.     regulator-always-on;
  2212.     regulator-boot-on;
  2213.     regulator-min-microvolt = <712500>;
  2214.     regulator-max-microvolt = <1450000>;
  2215.     regulator-ramp-delay = <12500>;
  2216.  
  2217.     regulator-state-mem {
  2218.      regulator-on-in-suspend;
  2219.      regulator-suspend-microvolt = <1000000>;
  2220.     };
  2221.    };
  2222.  
  2223.    vdd_arm: DCDC_REG2 {
  2224.     regulator-name = "vdd_arm";
  2225.     regulator-always-on;
  2226.     regulator-boot-on;
  2227.     regulator-min-microvolt = <712500>;
  2228.     regulator-max-microvolt = <1450000>;
  2229.     regulator-ramp-delay = <12500>;
  2230.  
  2231.     regulator-state-mem {
  2232.      regulator-on-in-suspend;
  2233.      regulator-suspend-microvolt = <950000>;
  2234.     };
  2235.    };
  2236.  
  2237.    vcc_ddr: DCDC_REG3 {
  2238.     regulator-name = "vcc_ddr";
  2239.     regulator-always-on;
  2240.     regulator-boot-on;
  2241.  
  2242.     regulator-state-mem {
  2243.      regulator-on-in-suspend;
  2244.     };
  2245.    };
  2246.  
  2247.    vcc_io: DCDC_REG4 {
  2248.     regulator-name = "vcc_io";
  2249.     regulator-always-on;
  2250.     regulator-boot-on;
  2251.     regulator-min-microvolt = <3300000>;
  2252.     regulator-max-microvolt = <3300000>;
  2253.  
  2254.     regulator-state-mem {
  2255.      regulator-on-in-suspend;
  2256.      regulator-suspend-microvolt = <3300000>;
  2257.     };
  2258.    };
  2259.  
  2260.    vcc_18: LDO_REG1 {
  2261.     regulator-name = "vcc_18";
  2262.     regulator-always-on;
  2263.     regulator-boot-on;
  2264.     regulator-min-microvolt = <1800000>;
  2265.     regulator-max-microvolt = <1800000>;
  2266.  
  2267.     regulator-state-mem {
  2268.      regulator-on-in-suspend;
  2269.      regulator-suspend-microvolt = <1800000>;
  2270.     };
  2271.    };
  2272.  
  2273.    vcc18_emmc: LDO_REG2 {
  2274.     regulator-name = "vcc18_emmc";
  2275.     regulator-always-on;
  2276.     regulator-boot-on;
  2277.     regulator-min-microvolt = <1800000>;
  2278.     regulator-max-microvolt = <1800000>;
  2279.  
  2280.     regulator-state-mem {
  2281.      regulator-on-in-suspend;
  2282.      regulator-suspend-microvolt = <1800000>;
  2283.     };
  2284.    };
  2285.  
  2286.    vdd_10: LDO_REG3 {
  2287.     regulator-name = "vdd_10";
  2288.     regulator-always-on;
  2289.     regulator-boot-on;
  2290.     regulator-min-microvolt = <1000000>;
  2291.     regulator-max-microvolt = <1000000>;
  2292.  
  2293.     regulator-state-mem {
  2294.      regulator-on-in-suspend;
  2295.      regulator-suspend-microvolt = <1000000>;
  2296.     };
  2297.    };
  2298.   };
  2299.  };
  2300. };
  2301.  
  2302. &io_domains {
  2303.  pmuio-supply = <&vcc_io>;
  2304.  vccio1-supply = <&vcc_io>;
  2305.  vccio2-supply = <&vcc18_emmc>;
  2306.  vccio3-supply = <&vcc_io>;
  2307.  vccio4-supply = <&vcc_io>;
  2308.  vccio5-supply = <&vcc_io>;
  2309.  vccio6-supply = <&vcc_io>;
  2310.  status = "okay";
  2311. };
  2312.  
  2313. &pinctrl {
  2314.  gmac2io {
  2315.   eth_phy_reset_pin: eth-phy-reset-pin {
  2316.    rockchip,pins = <1 18 0 &pcfg_pull_down>;
  2317.   };
  2318.  };
  2319.  
  2320.  leds {
  2321.   lan_led_pin: lan-led-pin {
  2322.    rockchip,pins = <2 15 0 &pcfg_pull_none>;
  2323.   };
  2324.  
  2325.   sys_led_pin: sys-led-pin {
  2326.    rockchip,pins = <3 21 0 &pcfg_pull_none>;
  2327.   };
  2328.  
  2329.   wan_led_pin: wan-led-pin {
  2330.    rockchip,pins = <2 18 0 &pcfg_pull_none>;
  2331.   };
  2332.  };
  2333.  
  2334.  lan {
  2335.   lan_vdd_pin: lan-vdd-pin {
  2336.    rockchip,pins = <2 22 0 &pcfg_pull_none>;
  2337.   };
  2338.  };
  2339.  
  2340.  pmic {
  2341.   pmic_int_l: pmic-int-l {
  2342.    rockchip,pins = <1 24 0 &pcfg_pull_up>;
  2343.   };
  2344.  };
  2345. };
  2346.  
  2347. &pwm2 {
  2348.  status = "okay";
  2349. };
  2350.  
  2351. &sdmmc {
  2352.  bus-width = <4>;
  2353.  cap-sd-highspeed;
  2354.  disable-wp;
  2355.  pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
  2356.  pinctrl-names = "default";
  2357.  vmmc-supply = <&vcc_sd>;
  2358.  status = "okay";
  2359. };
  2360.  
  2361. &spi0 {
  2362.  status = "okay";
  2363.  
  2364.  flash@0 {
  2365.   compatible = "jedec,spi-nor";
  2366.   reg = <0>;
  2367.   spi-max-frequency = <50000000>;
  2368.  };
  2369. };
  2370.  
  2371. &tsadc {
  2372.  rockchip,hw-tshut-mode = <0>;
  2373.  rockchip,hw-tshut-polarity = <0>;
  2374.  status = "okay";
  2375. };
  2376.  
  2377. &u2phy {
  2378.  status = "okay";
  2379. };
  2380.  
  2381. &u2phy_host {
  2382.  status = "okay";
  2383. };
  2384.  
  2385. &u2phy_otg {
  2386.  status = "okay";
  2387. };
  2388.  
  2389. &uart2 {
  2390.  status = "okay";
  2391. };
  2392.  
  2393. &usb20_otg {
  2394.  dr_mode = "host";
  2395.  status = "okay";
  2396. };
  2397.  
  2398. &usbdrd3 {
  2399.  dr_mode = "host";
  2400.  status = "okay";
  2401.  #address-cells = <1>;
  2402.  #size-cells = <0>;
  2403.  
  2404.  
  2405.  rtl8153: device@2 {
  2406.   compatible = "usbbda,8153";
  2407.   reg = <2>;
  2408.  };
  2409. };
  2410.  
  2411. &usb_host0_ehci {
  2412.  status = "okay";
  2413. };
  2414.  
  2415. &usb_host0_ohci {
  2416.  status = "okay";
  2417. };
  2418. # 11 "rk3328-orangepi-r1-plus-lts.dts" 2
  2419.  
  2420. / {
  2421.  model = "Xunlong Orange Pi R1 Plus LTS";
  2422.  compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
  2423. };
  2424.  
Tags: openwrt orangepi r1 plus lts
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