4

-- Interconnects
  -- A
  level_1_in_0 <= in0;
  level_1_in_1 <= in1;
  level_1_in_2 <= in2;
  level_1_in_3 <= in3;
  level_1_in_4 <= in4;
  level_1_in_5 <= in5;
  level_1_in_6 <= in6;
  level_1_in_7 <= in7;
  level_1_in_8 <= in8;
  level_1_in_9 <= in9;
  level_1_in_10 <= in10;
  level_1_in_11 <= in11;
  level_1_in_12 <= in12;
  level_1_in_13 <= in13;
  level_1_in_14 <= in14;
  level_1_in_15 <= in15;

-- B
  PROCESS(clk) BEGIN
    if rising_edge(clk) then
          level_2_in_0 <= level_1_out_0;
    level_2_in_1 <= level_1_out_1;
    level_2_in_2 <= level_1_out_2;
    level_2_in_3 <= level_1_out_3;
    level_2_in_4 <= level_1_out_4;
    level_2_in_5 <= level_1_out_5;
    level_2_in_6 <= level_1_out_6;
    level_2_in_7 <= level_1_out_7;
    level_2_in_8 <= level_1_out_8;
    level_2_in_9 <= level_1_out_9;
    level_2_in_10 <= level_1_out_10;
  end if;
end process;

    -- C
    level_3_in_0 <= level_2_out_0;
    level_3_in_1 <= level_2_out_1;
    level_3_in_2 <= level_2_out_2;
    level_3_in_3 <= level_2_out_3;
    level_3_in_4 <= level_2_out_4;
    level_3_in_5 <= level_2_out_5;
    level_3_in_6 <= level_2_out_6;
    level_3_in_7 <= level_2_out_7;


    -- D
    PROCESS(clk) BEGIN
      if rising_edge(clk) then
              level_4_in_0 <= level_3_out_0;
        level_4_in_1 <= level_3_out_1;
        level_4_in_2 <= level_3_out_2;
        level_4_in_3 <= level_3_out_3;
        level_4_in_4 <= level_3_out_4;
        level_4_in_5 <= level_3_out_5;
      end if;
    end process;

    -- E
    level_5_in_0 <= level_4_out_0;
    level_5_in_1 <= level_4_out_1;
    level_5_in_2 <= level_4_out_2;
    level_5_in_3 <= level_4_out_3;
    -- F

   PROCESS  (clk) BEGIN
   if rising_edge(clk) then
    level_6_in_0 <= level_5_out_0;
    level_6_in_1 <= level_5_out_1;
    level_6_in_2 <= level_5_out_2;
  end if;
  end process;

  outs <= outs_tmp;
  outc <= outc_tmp;

END csa_tree_behav;