VHDL Praktikum 2b

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
    port (
        reset_n     : in std_logic; -- Key 3
        clk         : in std_logic; --50 MHz
        switches        : in std_logic_vector(7 downto 0); -- zur Übernahme des ofl-values
        cnt_enable  : in std_logic; -- SW9
        ofl_rd      : in std_logic; -- read and store ofl-value, KEY0
        cnt_rd      : in std_logic; -- read and store the actual count-value, KEY1
        cnt_val_act : out std_logic_vector(7 downto 0); -- aktueller Zählwert
        cnt_val_stored_out : out std_logic_vector(7 downto 0) -- gespeicherter Zählwert
    );
end entity counter;

architecture arch of counter is

signal counter_50MHz: unsigned(22 downto 0);
signal counter_10Hz, overflow: unsigned(7 downto 0);

begin
    p: process(clk, reset_n)
    begin
        if (reset_n = '1') then
            counter_50MHz <= (others => '0');
            counter_10Hz <= (others => '0');
            cnt_val_act <= (others => '1');
            cnt_val_stored_out <= (others => '1');

        elsif (rising_edge(clk)) then
            if (cnt_enable = '1') then
                counter_50MHz <= counter_50MHz + 1;

                if (counter_50MHz >= 5000000) then
                    counter_50MHz <= (others => '0');
                    counter_10Hz <= counter_10Hz + 1;
                    cnt_val_act <= not std_logic_vector(counter_10Hz);
                end if;

                if (cnt_rd = '1') then
                    cnt_val_stored_out <= not std_logic_vector(counter_10Hz);
                end if;

                if (ofl_rd = '1') then
                    overflow <= unsigned(switches);
                end if;

                if (counter_10Hz >= overflow) then
                    counter_10Hz <= (others => '0');
                end if;
            end if;
        end if;

    end process p;
end architecture arch;