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Husi012

VHDL Praktikum 2b

Dec 12th, 2021 (edited)
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4.  
  5. entity counter is
  6.     port (
  7.         reset_n     : in std_logic; -- Key 3
  8.         clk         : in std_logic; --50 MHz
  9.         switches        : in std_logic_vector(7 downto 0); -- zur Übernahme des ofl-values
  10.         cnt_enable  : in std_logic; -- SW9
  11.         ofl_rd      : in std_logic; -- read and store ofl-value, KEY0
  12.         cnt_rd      : in std_logic; -- read and store the actual count-value, KEY1
  13.         cnt_val_act : out std_logic_vector(7 downto 0); -- aktueller Zählwert
  14.         cnt_val_stored_out : out std_logic_vector(7 downto 0) -- gespeicherter Zählwert
  15.     );
  16. end entity counter;
  17.  
  18. architecture arch of counter is
  19.  
  20. signal counter_50MHz: unsigned(22 downto 0);
  21. signal counter_10Hz, overflow: unsigned(7 downto 0);
  22.  
  23. begin
  24.     p: process(clk, reset_n)
  25.     begin
  26.         if (reset_n = '1') then
  27.             counter_50MHz <= (others => '0');
  28.             counter_10Hz <= (others => '0');
  29.             cnt_val_act <= (others => '1');
  30.             cnt_val_stored_out <= (others => '1');
  31.            
  32.         elsif (rising_edge(clk)) then
  33.             if (cnt_enable = '1') then
  34.                 counter_50MHz <= counter_50MHz + 1;
  35.                
  36.                 if (counter_50MHz >= 5000000) then
  37.                     counter_50MHz <= (others => '0');
  38.                     counter_10Hz <= counter_10Hz + 1;
  39.                     cnt_val_act <= not std_logic_vector(counter_10Hz);
  40.                 end if;
  41.                
  42.                 if (cnt_rd = '1') then
  43.                     cnt_val_stored_out <= not std_logic_vector(counter_10Hz);
  44.                 end if;
  45.                
  46.                 if (ofl_rd = '1') then
  47.                     overflow <= unsigned(switches);
  48.                 end if;
  49.                
  50.                 if (counter_10Hz >= overflow) then
  51.                     counter_10Hz <= (others => '0');
  52.                 end if;
  53.             end if;
  54.         end if;
  55.  
  56.     end process p;
  57. end architecture arch;
  58.    
  59.    
  60.    
  61.    
  62.    
  63.    
  64.    
  65.    
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