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-- Company:
-- Engineer:
--
-- Create Date:    07:58:40 10/18/2017
-- Design Name:
-- Module Name:    ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           f1 : in  STD_LOGIC;
           f0 : in  STD_LOGIC;
           Y : out  STD_LOGIC_VECTOR (4 downto 0));
end ALU;

architecture Behavioral of ALU is

begin

process(f0,f1)
  begin
  if f0='0' and f1='0' then
      Y<=A+B;
    elsif (f0='1' and f1='0') then
      Y<=A-B;
   elsif (f0='0' and f1='1') then
      Y<=A and B;
   elsif (f0='1' and f1='1') then
      Y<=A or B;
    end if;
   end process;


end Behavioral;

--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY ALU_test IS
END ALU_test;

ARCHITECTURE behavior OF ALU_test IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT ALU
    PORT(
         A : IN  std_logic_vector(3 downto 0);
         B : IN  std_logic_vector(3 downto 0);
         f1 : IN  std_logic;
         f0 : IN  std_logic;
         Y : OUT  std_logic_vector(4 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal A : std_logic_vector(3 downto 0) := (others => '0');
   signal B : std_logic_vector(3 downto 0) := (others => '0');
   signal f1 : std_logic := '0';
   signal f0 : std_logic := '0';

    --Outputs
   signal Y : std_logic_vector(4 downto 0);
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name
    BEGIN

 uut: ALU PORT MAP (
          A => A,
          B => B,
          f1 => f1,
          f0 => f0,
          Y => Y
        );

  -- constant <clock>_period : time := 10 ns;
       -- Clock process definitions

    --  <clock>_process :process
--   begin
    --  <clock> <= '0';
        --wait for <clock>_period/2;
        --<clock> <= '1';
        --wait for <clock>_period/2;
   --end process;


     -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
      wait for 100 ms;
     A<="0001";
      B<="1100";
      f1<='0';
      f0<='0';

     -- wait for <clock>_period*10;

      -- insert stimulus here

      wait;
   end process;



END;