API tools faq
paste
Advertisement
_dinsdale

imx6_ahci.c.rhaley.diff

_dinsdale
Jul 20th, 2017
226
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 10.40 KB | None | 0 0
raw download clone embed print report
  1. --- imx6_ahci.c 2017-07-19 20:12:00.974999000 -0700
  2. +++ /usr/home/russellh/FreeBSD/rh-armv6/src/sys/arm/freescale/imx/imx6_ahci.c 2017-07-19 20:18:18.460702000 -0700
  3. @@ -45,42 +45,44 @@ __FBSDID("$FreeBSD$");
  4. #include <arm/freescale/imx/imx_ccmvar.h>
  5. #include <arm/freescale/imx/imx6_ccmvar.h>
  6.  
  7. -#define SATA_P0PHYCR 0x00000178
  8. -#define SATA_P0PHYCR_CR_READ (1 << 19)
  9. -#define SATA_P0PHYCR_CR_WRITE (1 << 18)
  10. -#define SATA_P0PHYCR_CR_CAP_DATA (1 << 17)
  11. -#define SATA_P0PHYCR_CR_CAP_ADDR (1 << 16)
  12. -#define SATA_P0PHYCR_CR_DATA_IN(v) ((v) & 0xffff)
  13. -#define SATA_P0PHYSR 0x0000017c
  14. -#define SATA_P0PHYSR_CR_ACK (1 << 18)
  15. -#define SATA_P0PHYSR_CR_DATA_OUT(v) ((v) & 0xffff)
  16. +#define SATA_P0PHYCR 0x00000178
  17. +#define SATA_P0PHYCR_CR_READ (1 << 19)
  18. +#define SATA_P0PHYCR_CR_WRITE (1 << 18)
  19. +#define SATA_P0PHYCR_CR_CAP_DATA (1 << 17)
  20. +#define SATA_P0PHYCR_CR_CAP_ADDR (1 << 16)
  21. +#define SATA_P0PHYCR_CR_DATA_IN(v) ((v) & 0xffff)
  22. +#define SATA_P0PHYSR 0x0000017c
  23. +#define SATA_P0PHYSR_CR_ACK (1 << 18)
  24. +#define SATA_P0PHYSR_CR_DATA_OUT(v) ((v) & 0xffff)
  25.  
  26. -#define SATA_TIMER1MS 0x000000e0
  27. +#define SATA_TIMER1MS 0x000000e0
  28.  
  29. /* phy registers */
  30. -#define SATA_PHY_CLOCK_RESET 0x7f3f
  31. -#define SATA_PHY_CLOCK_RESET_RST (1 << 0)
  32. +#define SATA_PHY_CLOCK_RESET 0x7f3f
  33. +#define SATA_PHY_CLOCK_RESET_RST (1 << 0)
  34.  
  35. -#define SATA_PHY_LANE0_OUT_STAT 0x2003
  36. -#define SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE (1 << 1)
  37. +#define SATA_PHY_LANE0_OUT_STAT 0x2003
  38. +#define SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE (1 << 1)
  39.  
  40. +//imx6_ahci_phy_ctrl(struct ahci_controller* sc, uint32_t bitmask, int on)
  41. static int
  42. -imx6_ahci_phy_ctrl(struct ahci_controller* sc, uint32_t bitmask, int on)
  43. +imx6_ahci_phy_ctrl(struct ahci_controller* sc, uint32_t bitmask, bool on)
  44. {
  45. uint32_t v;
  46. int timeout;
  47.  
  48. v = ATA_INL(sc->r_mem, SATA_P0PHYCR);
  49. - if(on) {
  50. + if (on) {
  51. v |= bitmask;
  52. } else {
  53. v &= ~bitmask;
  54. }
  55. ATA_OUTL(sc->r_mem, SATA_P0PHYCR, v);
  56.  
  57. - for(timeout = 5000; timeout > 0; --timeout) {
  58. + for (timeout = 5000; timeout > 0; --timeout) {
  59. v = ATA_INL(sc->r_mem, SATA_P0PHYSR);
  60. - if(!!(v & SATA_P0PHYSR_CR_ACK) == !!on) {
  61. + //if (!!(v & SATA_P0PHYSR_CR_ACK) == !!on) {
  62. + if ((v & SATA_P0PHYSR_CR_ACK) == on) {
  63. break;
  64. }
  65. DELAY(100);
  66. @@ -97,23 +99,19 @@ static int
  67. imx6_ahci_phy_addr(struct ahci_controller* sc, uint32_t addr)
  68. {
  69. int error;
  70. +
  71. DELAY(100);
  72. -
  73. ATA_OUTL(sc->r_mem, SATA_P0PHYCR, addr);
  74.  
  75. - error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, 1);
  76. - if(error != 0) {
  77. - if(bootverbose) {
  78. - device_printf(sc->dev, "%s: timeout on SATA_P0PHYCR_CR_CAP_ADDR=1\n", __FUNCTION__);
  79. - }
  80. + error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, true);
  81. + if (error != 0) {
  82. + device_printf(sc->dev, "%s: timeout on SATA_P0PHYCR_CR_CAP_ADDR=1\n", __FUNCTION__);
  83. return error;
  84. }
  85.  
  86. - error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, 0);
  87. - if(error != 0) {
  88. - if(bootverbose) {
  89. - device_printf(sc->dev, "%s: timeout on SATA_P0PHYCR_CR_CAP_ADDR=0\n", __FUNCTION__);
  90. - }
  91. + error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, false);
  92. + if (error != 0) {
  93. + device_printf(sc->dev, "%s: timeout on SATA_P0PHYCR_CR_CAP_ADDR=0\n", __FUNCTION__);
  94. return error;
  95. }
  96.  
  97. @@ -127,43 +125,39 @@ imx6_ahci_phy_write(struct ahci_controller* sc, uint32
  98. int error;
  99.  
  100. error = imx6_ahci_phy_addr(sc, addr);
  101. - if(error != 0) {
  102. - if(bootverbose) { device_printf(sc->dev, "%s: error on imx6_ahci_phy_addr\n", __FUNCTION__); }
  103. + if (error != 0) {
  104. + device_printf(sc->dev, "%s: error on imx6_ahci_phy_addr\n", __FUNCTION__);
  105. return error;
  106. }
  107.  
  108. ATA_OUTL(sc->r_mem, SATA_P0PHYCR, data);
  109.  
  110. - error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, 1);
  111. - if(error != 0) {
  112. - if(bootverbose) {
  113. - device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_CAP_DATA=1\n", __FUNCTION__);
  114. - }
  115. + error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, true);
  116. + if (error != 0) {
  117. + device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_CAP_DATA=1\n", __FUNCTION__);
  118. return error;
  119. }
  120. - if(imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, 0) != 0) {
  121. - if(bootverbose) {
  122. - device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_CAP_DATA=0\n", __FUNCTION__);
  123. - }
  124. + if (imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, false) != 0) {
  125. + device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_CAP_DATA=0\n", __FUNCTION__);
  126. return error;
  127. }
  128.  
  129. - if((addr == SATA_PHY_CLOCK_RESET) && data) {
  130. + if ((addr == SATA_PHY_CLOCK_RESET) && data) {
  131. /* we can't check ACK after RESET */
  132. ATA_OUTL(sc->r_mem, SATA_P0PHYCR,
  133. SATA_P0PHYCR_CR_DATA_IN(data) | SATA_P0PHYCR_CR_WRITE);
  134. return 0;
  135. }
  136.  
  137. - error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, 1);
  138. - if(error != 0) {
  139. - if(bootverbose) { device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_WRITE=1\n", __FUNCTION__); }
  140. + error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, true);
  141. + if (error != 0) {
  142. + device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_WRITE=1\n", __FUNCTION__);
  143. return error;
  144. }
  145.  
  146. - error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, 0);
  147. - if(error != 0) {
  148. - if(bootverbose) { device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_WRITE=0\n", __FUNCTION__); }
  149. + error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, false);
  150. + if (error != 0) {
  151. + device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_WRITE=0\n", __FUNCTION__);
  152. return error;
  153. }
  154.  
  155. @@ -177,22 +171,22 @@ imx6_ahci_phy_read(struct ahci_controller* sc, uint32_
  156. uint32_t v;
  157.  
  158. error = imx6_ahci_phy_addr(sc, addr);
  159. - if(error != 0) {
  160. - if(bootverbose) { device_printf(sc->dev, "%s: error on imx6_ahci_phy_addr\n", __FUNCTION__); }
  161. + if (error != 0) {
  162. + device_printf(sc->dev, "%s: error on imx6_ahci_phy_addr\n", __FUNCTION__);
  163. return error;
  164. }
  165.  
  166. - error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_READ, 1);
  167. - if(error != 0) {
  168. - if(bootverbose) { device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_READ=1\n", __FUNCTION__); }
  169. + error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_READ, true);
  170. + if (error != 0) {
  171. + device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_READ=1\n", __FUNCTION__);
  172. return error;
  173. }
  174.  
  175. v = ATA_INL(sc->r_mem, SATA_P0PHYSR);
  176.  
  177. - error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_READ, 0);
  178. - if(error != 0) {
  179. - if(bootverbose) { device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_READ=0\n", __FUNCTION__); }
  180. + error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_READ, false);
  181. + if (error != 0) {
  182. + device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_READ=0\n", __FUNCTION__);
  183. return error;
  184. }
  185.  
  186. @@ -202,9 +196,11 @@ imx6_ahci_phy_read(struct ahci_controller* sc, uint32_
  187. static int
  188. imx6_ahci_probe(device_t dev)
  189. {
  190. - if(!ofw_bus_is_compatible(dev, "fsl,imx6q-ahci")) {
  191. + if (!ofw_bus_status_okay(dev))
  192. return (ENXIO);
  193. - }
  194. + if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ahci"))
  195. + return (ENXIO);
  196. +
  197. device_set_desc(dev, "i.MX6 Integrated AHCI controller");
  198.  
  199. return (BUS_PROBE_DEFAULT);
  200. @@ -215,9 +211,7 @@ imx6_ahci_attach(device_t dev)
  201. {
  202. struct ahci_controller* ctlr;
  203. uint32_t v;
  204. - int timeout;
  205. - int pllstat;
  206. - int error;
  207. + int error, pllstat, timeout;
  208.  
  209. /*
  210. * Init the device PHY
  211. @@ -225,7 +219,7 @@ imx6_ahci_attach(device_t dev)
  212. ctlr = device_get_softc(dev);
  213.  
  214. error = imx6_ccm_sataphy_enable();
  215. - if(error != 0) {
  216. + if (error != 0) {
  217. device_printf(dev, "time out resetting AHCI PHY\n");
  218. return error;
  219. }
  220. @@ -236,54 +230,55 @@ imx6_ahci_attach(device_t dev)
  221. ctlr->subdeviceid = 0;
  222. ctlr->numirqs = 1;
  223. ctlr->r_rid = 0;
  224. - if(!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
  225. - &ctlr->r_rid, RF_ACTIVE))) {
  226. +
  227. + if ((ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
  228. + &ctlr->r_rid, RF_ACTIVE)) != NULL)
  229. return (ENXIO);
  230. - }
  231.  
  232. v = imx_iomux_gpr_get(IOMUX_GPR13);
  233. - v &= ~(IOMUX_GPR13_SATA_PHY_8(7) |
  234. + v &= ~(IOMUX_GPR13_SATA_PHY_8(7) |
  235. IOMUX_GPR13_SATA_PHY_7(0x1f) |
  236. - IOMUX_GPR13_SATA_PHY_6(7) |
  237. - IOMUX_GPR13_SATA_SPEED(1) |
  238. - IOMUX_GPR13_SATA_PHY_5(1) |
  239. - IOMUX_GPR13_SATA_PHY_4(7) |
  240. - IOMUX_GPR13_SATA_PHY_3(0xf) |
  241. + IOMUX_GPR13_SATA_PHY_6(7) |
  242. + IOMUX_GPR13_SATA_SPEED(1) |
  243. + IOMUX_GPR13_SATA_PHY_5(1) |
  244. + IOMUX_GPR13_SATA_PHY_4(7) |
  245. + IOMUX_GPR13_SATA_PHY_3(0xf) |
  246. IOMUX_GPR13_SATA_PHY_2(0x1f) |
  247. - IOMUX_GPR13_SATA_PHY_1(1) |
  248. + IOMUX_GPR13_SATA_PHY_1(1) |
  249. IOMUX_GPR13_SATA_PHY_0(1));
  250. /* setting */
  251. - v |= IOMUX_GPR13_SATA_PHY_8(5) | /* Rx 3.0db */
  252. - IOMUX_GPR13_SATA_PHY_7(0x12) | /* Rx SATA2m */
  253. - IOMUX_GPR13_SATA_PHY_6(3) | /* Rx DPLL mode */
  254. - IOMUX_GPR13_SATA_SPEED(1) | /* 3.0GHz */
  255. - IOMUX_GPR13_SATA_PHY_5(0) | /* SpreadSpectram */
  256. - IOMUX_GPR13_SATA_PHY_4(4) | /* Tx Attenuation 9/16 */
  257. - IOMUX_GPR13_SATA_PHY_3(0) | /* Tx Boost 0db */
  258. - IOMUX_GPR13_SATA_PHY_2(0x11) | /* Tx Level 1.104V */
  259. + v |= IOMUX_GPR13_SATA_PHY_8(5) | /* Rx 3.0db */
  260. + IOMUX_GPR13_SATA_PHY_7(0x12) | /* Rx SATA2m */
  261. + IOMUX_GPR13_SATA_PHY_6(3) | /* Rx DPLL mode */
  262. + IOMUX_GPR13_SATA_SPEED(1) | /* 3.0GHz */
  263. + IOMUX_GPR13_SATA_PHY_5(0) | /* SpreadSpectram */
  264. + IOMUX_GPR13_SATA_PHY_4(4) | /* Tx Attenuation 9/16 */
  265. + IOMUX_GPR13_SATA_PHY_3(0) | /* Tx Boost 0db */
  266. + IOMUX_GPR13_SATA_PHY_2(0x11) | /* Tx Level 1.104V */
  267. IOMUX_GPR13_SATA_PHY_1(1); /* PLL clock enable */
  268. +
  269. imx_iomux_gpr_set(IOMUX_GPR13, v);
  270.  
  271. /* phy reset */
  272. error = imx6_ahci_phy_write(ctlr, SATA_PHY_CLOCK_RESET,
  273. SATA_PHY_CLOCK_RESET_RST);
  274. - if(error != 0) {
  275. + if (error != 0) {
  276. device_printf(dev, "cannot reset PHY\n");
  277. goto fail;
  278. }
  279.  
  280. - for(timeout = 50; timeout > 0; --timeout) {
  281. + for (timeout = 50; timeout > 0; --timeout) {
  282. DELAY(100);
  283. pllstat = imx6_ahci_phy_read(ctlr, SATA_PHY_LANE0_OUT_STAT);
  284. - if(pllstat < 0) {
  285. + if (pllstat < 0) {
  286. device_printf(dev, "cannot read LANE0 status\n");
  287. break;
  288. }
  289. - if(pllstat & SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE) {
  290. + if (pllstat & SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE)
  291. break;
  292. - }
  293. }
  294. - if(timeout <= 0) {
  295. +
  296. + if (timeout <= 0) {
  297. device_printf(dev, "time out reading LANE0 status\n");
  298. error = ETIMEDOUT;
  299. goto fail;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!