library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clock_divider is
    port
    (
        mclk: in std_logic; -- master clock, set to pin V10
        switch: out std_logic_vector(1 downto 0) -- output of divided clock
    );
end clock_divider;

architecture Behavioral of clock_divider is
    -- change this if you need to increase the size of the counter vector
    signal counter : std_logic_vector(10 downto 0) := (others => '0');
begin

    process (mclk)  -- using the system clock
    begin
        if mclk = '1' and mclk'Event then
            counter <= counter +1;
        end if;
    end process;

    -- if you want a longer delay, use a higher set of numbers here.
    -- if you are trying to simulation, use a lower number (like 1 downto 0)
    switch <= counter(10 downto 9);

end Behavioral;