mux_4_to_1

-- mux 4x1 em VHDL
-- entradas A0,A1,A2 e A3
-- saída s
-- entradas de selação Sel0 e sel1
--
-- selo sel 1   s=Ai,  i variando de 0 a 3
-- ---------------
--  0   0       A(0)
--  0   1       A(1)
--  1   0       A(2)
--  1   1       A(3)

--Autor: Marcos Meira

--data :09 de agosto de 2016


 Library IEEE;
 use IEEE.std_logic_1164.all;

 entity mux_4_to_1 is
 port (
       sel : in std_logic_vector (1 downto 0);
       A   : in std_logic_vector (3 downto 0);
       s   : out std_logic

      );
 end mux_4_to_1;

 architecture hardware of mux_4_to_1 is
 begin

          with sel select

                     s <= A(0) when "00",
                          A(1) when "01",
                          A(2) when "10",
                          A(3) when "11",
                          '0'  when others;
end hardware;