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  1. Index: src/southbridge/intel/i82371eb/i82371eb_fadt.c
  2. ===================================================================
  3. --- src/southbridge/intel/i82371eb/i82371eb_fadt.c      (revision 0)
  4. +++ src/southbridge/intel/i82371eb/i82371eb_fadt.c      (revision 0)
  5. @@ -0,0 +1,167 @@
  6. +// copied from src/southbridge/via/vt8237r/vt8237_fadt.c
  7. +
  8. +/*
  9. + * This file is part of the coreboot project.
  10. + *
  11. + * Copyright (C) 2004 Nick Barker <nick.barker9@btinternet.com>
  12. + * Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz>
  13. + *
  14. + * This program is free software; you can redistribute it and/or modify
  15. + * it under the terms of the GNU General Public License as published by
  16. + * the Free Software Foundation; either version 2 of the License, or
  17. + * (at your option) any later version.
  18. + *
  19. + * This program is distributed in the hope that it will be useful,
  20. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22. + * GNU General Public License for more details.
  23. + *
  24. + * You should have received a copy of the GNU General Public License
  25. + * along with this program; if not, write to the Free Software
  26. + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  27. + */
  28. +
  29. +#include <string.h>
  30. +#include <arch/acpi.h>
  31. +#include <device/device.h>
  32. +#include <device/pci.h>
  33. +/*
  34. +PCI_VENDOR_ID_INTEL,
  35. +PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI
  36. +*/
  37. +#include <device/pci_ids.h>
  38. +#include "i82371eb.h" /* PM_IO_BASE */
  39. +
  40. +/**
  41. + * Create the Fixed ACPI Description Tables (FADT) for any board with this SB.
  42. + */
  43. +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
  44. +{
  45. +       acpi_header_t *header = &(fadt->header);
  46. +       device_t dev;
  47. +
  48. +       /* Power management controller */
  49. +       dev = dev_find_device(PCI_VENDOR_ID_INTEL,
  50. +                               PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0); /* pci_ids.h */
  51. +
  52. +       memset((void *) fadt, 0, sizeof(acpi_fadt_t));
  53. +       memcpy(header->signature, "FACP", 4);
  54. +       header->length = 244;
  55. +       header->revision = 4;
  56. +       memcpy(header->oem_id, "COREBO", 6);
  57. +       memcpy(header->oem_table_id, "COREBOOT", 8);
  58. +       memcpy(header->asl_compiler_id, "CORE", 4);
  59. +       header->asl_compiler_revision = 42;
  60. +
  61. +       fadt->firmware_ctrl = (u32)facs;
  62. +       fadt->dsdt = (u32)dsdt;
  63. +       fadt->preferred_pm_profile = 0;
  64. +       fadt->sci_int = 9;
  65. +       fadt->smi_cmd = 0;
  66. +       fadt->acpi_enable = 0;
  67. +       fadt->acpi_disable = 0;
  68. +       fadt->s4bios_req = 0x0;
  69. +       fadt->pstate_cnt = 0x0;
  70. +
  71. +       fadt->pm1a_evt_blk = PM_IO_BASE; /* i82371eb.h */
  72. +//     fadt->pm1b_evt_blk = PM_IO_BASE;
  73. +       fadt->pm1a_cnt_blk = PM_IO_BASE + PMCNTRL; // 0x4
  74. +//     fadt->pm1b_cnt_blk = 0x0;
  75. +       fadt->pm_tmr_blk = PM_IO_BASE + PMTMR; // 0x8
  76. +       fadt->gpe0_blk = PM_IO_BASE + GPSTS; // 0xc
  77. +//     fadt->gpe1_blk = 0x0;
  78. +//     fadt->gpe1_base = 0;
  79. +//     fadt->gpe1_blk_len = 0;
  80. +
  81. +       fadt->pm1_evt_len = 4;
  82. +       fadt->pm1_cnt_len = 2;
  83. +//     fadt->pm2_cnt_len = 0;
  84. +       fadt->pm_tmr_len = 4;
  85. +       fadt->gpe0_blk_len = 4;
  86. +
  87. +       fadt->cst_cnt = 0;
  88. +       fadt->p_lvl2_lat = 90;
  89. +       fadt->p_lvl3_lat = 900;
  90. +       fadt->flush_size = 0;
  91. +       fadt->flush_stride = 0;
  92. +       fadt->duty_offset = 0;
  93. +       fadt->duty_width = 1;   //??
  94. +       fadt->day_alrm = 0x7d;
  95. +       fadt->mon_alrm = 0x7e;
  96. +       fadt->century = 0x32;
  97. +       /* We have legacy devices, 8042, VGA is ok to probe, MSI are not supported */
  98. +       fadt->iapc_boot_arch = 0xb;
  99. +       /* check me */
  100. +       fadt->flags = 0xa5;
  101. +
  102. +       fadt->reset_reg.space_id = 0;
  103. +       fadt->reset_reg.bit_width = 0;
  104. +       fadt->reset_reg.bit_offset = 0;
  105. +       fadt->reset_reg.resv = 0;
  106. +       fadt->reset_reg.addrl = 0x0;
  107. +       fadt->reset_reg.addrh = 0x0;
  108. +
  109. +       fadt->reset_value = 0;
  110. +       fadt->x_firmware_ctl_l = (u32)facs;
  111. +       fadt->x_firmware_ctl_h = 0;
  112. +       fadt->x_dsdt_l = (u32)dsdt;
  113. +       fadt->x_dsdt_h = 0;
  114. +
  115. +       fadt->x_pm1a_evt_blk.space_id = 1;
  116. +       fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
  117. +       fadt->x_pm1a_evt_blk.bit_offset = 0;
  118. +       fadt->x_pm1a_evt_blk.resv = 0;
  119. +       fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
  120. +       fadt->x_pm1a_evt_blk.addrh = 0x0;
  121. +
  122. +//     fadt->x_pm1b_evt_blk.space_id = 1;
  123. +//     fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8;
  124. +//     fadt->x_pm1b_evt_blk.bit_offset = 0;
  125. +//     fadt->x_pm1b_evt_blk.resv = 0;
  126. +//     fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
  127. +//     fadt->x_pm1b_evt_blk.addrh = 0x0;
  128. +
  129. +       fadt->x_pm1a_cnt_blk.space_id = 1;
  130. +       fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
  131. +       fadt->x_pm1a_cnt_blk.bit_offset = 0;
  132. +       fadt->x_pm1a_cnt_blk.resv = 0;
  133. +       fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
  134. +       fadt->x_pm1a_cnt_blk.addrh = 0x0;
  135. +
  136. +//     fadt->x_pm1b_cnt_blk.space_id = 1;
  137. +//     fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
  138. +//     fadt->x_pm1b_cnt_blk.bit_offset = 0;
  139. +//     fadt->x_pm1b_cnt_blk.resv = 0;
  140. +//     fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
  141. +//     fadt->x_pm1b_cnt_blk.addrh = 0x0;
  142. +
  143. +//     fadt->x_pm2_cnt_blk.space_id = 1;
  144. +//     fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
  145. +//     fadt->x_pm2_cnt_blk.bit_offset = 0;
  146. +//     fadt->x_pm2_cnt_blk.resv = 0;
  147. +//     fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
  148. +//     fadt->x_pm2_cnt_blk.addrh = 0x0;
  149. +
  150. +       fadt->x_pm_tmr_blk.space_id = 1;
  151. +       fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
  152. +       fadt->x_pm_tmr_blk.bit_offset = 0;
  153. +       fadt->x_pm_tmr_blk.resv = 0;
  154. +       fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
  155. +       fadt->x_pm_tmr_blk.addrh = 0x0;
  156. +
  157. +       fadt->x_gpe0_blk.space_id = 1;
  158. +       fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
  159. +       fadt->x_gpe0_blk.bit_offset = 0;
  160. +       fadt->x_gpe0_blk.resv = 0;
  161. +       fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
  162. +       fadt->x_gpe0_blk.addrh = 0x0;
  163. +
  164. +//     fadt->x_gpe1_blk.space_id = 1;
  165. +//     fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;;
  166. +//     fadt->x_gpe1_blk.bit_offset = 0;
  167. +//     fadt->x_gpe1_blk.resv = 0;
  168. +//     fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
  169. +//     fadt->x_gpe1_blk.addrh = 0x0;
  170. +
  171. +       header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
  172. +}
  173. Index: src/southbridge/intel/i82371eb/Makefile.inc
  174. ===================================================================
  175. --- src/southbridge/intel/i82371eb/Makefile.inc (revision 5402)
  176. +++ src/southbridge/intel/i82371eb/Makefile.inc (working copy)
  177. @@ -26,3 +26,4 @@
  178.  driver-y +=  i82371eb_reset.o
  179.  
  180.  #initobj-y += i82371eb_early_rom.o
  181. +obj-$(CONFIG_HAVE_ACPI_TABLES) += i82371eb_fadt.o
  182. Index: src/southbridge/intel/i82371eb/i82371eb.h
  183. ===================================================================
  184. --- src/southbridge/intel/i82371eb/i82371eb.h   (revision 5402)
  185. +++ src/southbridge/intel/i82371eb/i82371eb.h   (working copy)
  186. @@ -54,7 +54,26 @@
  187.  /* Power management (ACPI) */
  188.  #define PMBA           0x40    /* Power management base address */
  189.  #define PMREGMISC      0x80    /* Miscellaneous power management */
  190. +#define PMCNTRL                0x04    /* Power Management Control */
  191. +#define PMTMR          0x08    /* Power Management Timer */
  192. +#define GPSTS          0x0c    /* General Purpose Status */
  193.  
  194. +/* Device resources */
  195. +#define DEVRESA                0x5c    /* Device Resource A */
  196. +#define DEVRESB                0x60    /* Device Resource B */
  197. +#define DEVRESC                0x64    /* Device Resource C */
  198. +#define DEVRESD                0x50    /* Device Resource D */
  199. +#define DEVRESE                0x68    /* Device Resource E */
  200. +#define DEVRESF                0x6c    /* Device Resource F */
  201. +#define DEVRESG                0x70    /* Device Resource G */
  202. +#define DEVRESH                0x74    /* Device Resource H */
  203. +#define DEVRESI                0x78    /* Device Resource I */
  204. +#define DEVRESJ                0x7c    /* Device Resource J */
  205. +
  206. +/* Device activity */
  207. +#define DEVACTA                0x54    /* Device Activity A */
  208. +#define DEVACTB                0x58    /* Device Activity B */
  209. +
  210.  /* Bit definitions */
  211.  #define EXT_BIOS_ENABLE_1MB    (1 << 9)  /* 1-Meg Extended BIOS Enable */
  212.  #define EXT_BIOS_ENABLE                (1 << 7)  /* Extended BIOS Enable */
  213. @@ -73,4 +92,7 @@
  214.  #define ISA                    (1 << 0)  /* Select ISA */
  215.  #define EIO                    (0 << 0)  /* Select EIO */
  216.  
  217. +/* Power Management Base Address */
  218. +#define PM_IO_BASE 0xe400
  219. +
  220.  #endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */
  221. Index: src/southbridge/intel/i82371eb/i82371eb_smbus.c
  222. ===================================================================
  223. --- src/southbridge/intel/i82371eb/i82371eb_smbus.c     (revision 5402)
  224. +++ src/southbridge/intel/i82371eb/i82371eb_smbus.c     (working copy)
  225. @@ -2,6 +2,7 @@
  226.   * This file is part of the coreboot project.
  227.   *
  228.   * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
  229. + * Copyright (C) 2010 Keith Hui <buurin@gmail.com>
  230.   *
  231.   * This program is free software; you can redistribute it and/or modify
  232.   * it under the terms of the GNU General Public License as published by
  233. @@ -25,7 +26,57 @@
  234.  #include <device/smbus.h>
  235.  #include "i82371eb.h"
  236.  
  237. -/* TODO: Needed later? */
  238. +/* Table format: register, bitmask, value. */
  239. +static const u8 register_values[] = {
  240. +       /* DEVRESE - Device Resource E
  241. +        * 0x68 - 0x6A
  242. +        *
  243. +        * [23:21] Reserved
  244. +        * [20:20] Device 12 I/O Monitor Enable (IO_EN_DEV12)
  245. +        *         0 = Enable PCI bus decode for accesses to the I/O address
  246. +        *             range selected by the IBASE_DEV12 and IMASK_DEV12 fields
  247. +        *         1 = Disable
  248. +        * [19:16] Device 12 I/O Decode Mask (IMASK_DEV12)
  249. +        *         Specifies the 4-bit I/O base address mask used to determine
  250. +        *         the IO address range size for device 12 accesses.
  251. +        *         IMASK_DEV12 (bits[19:16]) correspond to AD[3:0]. A '1' in a
  252. +        *         bit position indicates that the corresponding address bit is
  253. +        *         masked (i.e. ignored) when performing the decode. Note that
  254. +        *         programming these bits to certain patterns (such as '1001')
  255. +        *         results in a split address range.
  256. +        * [15:00] Device 12 I/O Decode Base Address (IBASE_DEV12)
  257. +        *         Specifies the 16-bit I/O base address range (AD[15:0]) for the
  258. +        *         device 12 I/O range. When this field is combined with IMASK_DEV12
  259. +        *         field, an I/O range is defined starting from the base address
  260. +        *         register value to the size defined by the mask register.
  261. +        */
  262. +       // Set device 12 I/O range at 0xe404-0xe405 and enable.
  263. +       DEVRESE + 0, 0x00, 0x04,
  264. +       DEVRESE + 1, 0x00, 0xe4,
  265. +       DEVRESE + 2, 0x00, 0x11,
  266. +};
  267. +
  268. +static void pwrmgt_init(struct device *dev)
  269. +{
  270. +       int i, max;
  271. +       u8 reg;
  272. +
  273. +       /* Sets the base address of power management ports. */
  274. +       pci_write_config16(dev, PMBA, PM_IO_BASE | 1);
  275. +
  276. +       /* Initialize other aspects of PIIX4 power management,
  277. +        * using the same approach in i440bx/raminit.c. */
  278. +       max = sizeof(register_values);
  279. +
  280. +       /* Set registers as specified in the register_values[] array. */
  281. +       for (i = 0; i < max; i += 3) {
  282. +               reg = pci_read_config8(dev, register_values[i]);
  283. +               reg &= register_values[i + 1];
  284. +               reg |= register_values[i + 2];
  285. +               pci_write_config8(dev, register_values[i], reg);
  286. +       }
  287. +}
  288. +
  289.  static const struct smbus_bus_operations lops_smbus_bus = {
  290.  };
  291.  
  292. @@ -33,7 +84,7 @@
  293.         .read_resources         = pci_dev_read_resources,
  294.         .set_resources          = pci_dev_set_resources,
  295.         .enable_resources       = pci_dev_enable_resources,
  296. -       .init                   = 0,
  297. +       .init                   = pwrmgt_init,
  298.         .scan_bus               = scan_static_bus,
  299.         .enable                 = 0,
  300.         .ops_pci                = 0, /* No subsystem IDs on 82371EB! */
  301. Index: src/mainboard/asus/p2b/Kconfig
  302. ===================================================================
  303. --- src/mainboard/asus/p2b/Kconfig      (revision 5402)
  304. +++ src/mainboard/asus/p2b/Kconfig      (working copy)
  305. @@ -27,6 +27,7 @@
  306.         select SUPERIO_WINBOND_W83977TF
  307.         select ROMCC
  308.         select HAVE_PIRQ_TABLE
  309. +       select HAVE_ACPI_TABLES
  310.         select UDELAY_TSC
  311.         select BOARD_ROMSIZE_KB_256
  312.  
  313. Index: src/mainboard/asus/p2b/devicetree.cb
  314. ===================================================================
  315. --- src/mainboard/asus/p2b/devicetree.cb        (revision 5402)
  316. +++ src/mainboard/asus/p2b/devicetree.cb        (working copy)
  317. @@ -50,10 +50,10 @@
  318.        register "ide1_enable" = "1"
  319.        register "ide_legacy_enable" = "1"
  320.        # Enable UDMA/33 for higher speed if your IDE device(s) support it.
  321. -      register "ide0_drive0_udma33_enable" = "0"
  322. -      register "ide0_drive1_udma33_enable" = "0"
  323. -      register "ide1_drive0_udma33_enable" = "0"
  324. -      register "ide1_drive1_udma33_enable" = "0"
  325. +      register "ide0_drive0_udma33_enable" = "1"
  326. +      register "ide0_drive1_udma33_enable" = "1"
  327. +      register "ide1_drive0_udma33_enable" = "1"
  328. +      register "ide1_drive1_udma33_enable" = "1"
  329.      end
  330.    end
  331.  end
  332. Index: src/mainboard/asus/p2b/romstage.c
  333. ===================================================================
  334. --- src/mainboard/asus/p2b/romstage.c   (revision 5402)
  335. +++ src/mainboard/asus/p2b/romstage.c   (working copy)
  336. @@ -62,10 +62,12 @@
  337.         i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
  338.  
  339.         enable_smbus();
  340. -       /* dump_spd_registers(); */
  341. +       dump_spd_registers();
  342.         sdram_set_registers();
  343.         sdram_set_spd_registers();
  344.         sdram_enable();
  345. -       /* ram_check(0, 640 * 1024); */
  346. +       ram_check(0, 640 * 1024);
  347. +       //ram_check(64 * 1024 * 1024, 640 + (64 * 1024 * 1024));
  348. +       //ram_check(256 * 1024 *1024, 640 + (256 * 1024 * 1024));
  349.  }
  350.  
  351. Index: src/mainboard/asus/p2b/acpi_tables.c
  352. ===================================================================
  353. --- src/mainboard/asus/p2b/acpi_tables.c        (revision 0)
  354. +++ src/mainboard/asus/p2b/acpi_tables.c        (revision 0)
  355. @@ -0,0 +1,176 @@
  356. +// copied from src/mainboard/asus/a8v-e_se/acpi_tables.c
  357. +
  358. +/*
  359. + * This file is part of the coreboot project.
  360. + *
  361. + * Written by Stefan Reinauer <stepan@openbios.org>.
  362. + * ACPI FADT, FACS, and DSDT table support added by
  363. + *
  364. + * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
  365. + * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
  366. + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
  367. + *
  368. + * This program is free software; you can redistribute it and/or modify
  369. + * it under the terms of the GNU General Public License as published by
  370. + * the Free Software Foundation; version 2 of the License.
  371. + *
  372. + * This program is distributed in the hope that it will be useful,
  373. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  374. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  375. + * GNU General Public License for more details.
  376. + *
  377. + * You should have received a copy of the GNU General Public License
  378. + * along with this program; if not, write to the Free Software
  379. + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  380. + */
  381. +
  382. +#include <console/console.h>
  383. +#include <string.h>
  384. +#include <arch/acpi.h>
  385. +#include <arch/smp/mpspec.h>
  386. +#include <device/device.h>
  387. +#include <device/pci_ids.h>
  388. +//#include <../../../southbridge/via/vt8237r/vt8237r.h>
  389. +//#include <../../../southbridge/via/k8t890/k8t890.h>
  390. +
  391. +extern const unsigned char AmlCode[];
  392. +
  393. +unsigned long acpi_fill_slit(unsigned long current)
  394. +{
  395. +       // Not implemented
  396. +       return current;
  397. +}
  398. +
  399. +unsigned long acpi_fill_srat(unsigned long current)
  400. +{
  401. +       // Not implemented
  402. +       return current;
  403. +}
  404. +
  405. +//unsigned long acpi_fill_fadt(unsigned long current)
  406. +//{
  407. +       // Not implemented
  408. +//     return current;
  409. +//}
  410. +
  411. +unsigned long acpi_fill_mcfg(unsigned long current)
  412. +{
  413. +//     device_t dev;
  414. +//     struct resource *res;
  415. +//
  416. +//     dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0);
  417. +//     dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0); // pci_ids.h
  418. +//     if (!dev)
  419. +//             return current;
  420. +//
  421. +//     res = find_resource(dev, K8T890_MMCONFIG_MBAR);
  422. +//     if (res) {
  423. +//             current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)
  424. +//                             current, res->base, 0x0, 0x0, 0xff);
  425. +//     }
  426. +       return current;
  427. +}
  428. +
  429. +unsigned long acpi_fill_madt(unsigned long current)
  430. +{
  431. +//     unsigned int gsi_base = 0x18;
  432. +//
  433. +       /* Create all subtables for processors. */
  434. +//     current = acpi_create_madt_lapics(current);
  435. +//
  436. +       /* Write SB IOAPIC. */
  437. +//     current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
  438. +//                             VT8237R_APIC_ID, VT8237R_APIC_BASE, 0);
  439. +//
  440. +       /* Write NB IOAPIC. */
  441. +//     current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
  442. +//                             K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
  443. +//
  444. +       /* IRQ9 ACPI active low. */
  445. +//     current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
  446. +//             current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
  447. +//
  448. +       /* IRQ0 -> APIC IRQ2. */
  449. +//     current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
  450. +//                                             current, 0, 0, 2, 0x0);
  451. +//
  452. +       /* Create all subtables for processors. */
  453. +//     current = acpi_create_madt_lapic_nmis(current,
  454. +//                     MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
  455. +//
  456. +       return current;
  457. +}
  458. +
  459. +unsigned long write_acpi_tables(unsigned long start)
  460. +{
  461. +       unsigned long current;
  462. +       acpi_rsdp_t *rsdp;
  463. +       acpi_srat_t *srat;
  464. +       acpi_rsdt_t *rsdt;
  465. +       acpi_madt_t *madt;
  466. +       acpi_mcfg_t *mcfg;
  467. +       acpi_fadt_t *fadt;
  468. +       acpi_facs_t *facs;
  469. +       acpi_header_t *dsdt;
  470. +
  471. +       /* Align ACPI tables to 16 byte. */
  472. +       start = (start + 0x0f) & -0x10;
  473. +       current = start;
  474. +
  475. +       printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
  476. +
  477. +       /* We need at least an RSDP and an RSDT table. */
  478. +       rsdp = (acpi_rsdp_t *) current;
  479. +       current += sizeof(acpi_rsdp_t);
  480. +       rsdt = (acpi_rsdt_t *) current;
  481. +       current += sizeof(acpi_rsdt_t);
  482. +
  483. +       /* Clear all table memory. */
  484. +       memset((void *) start, 0, current - start);
  485. +
  486. +       acpi_write_rsdp(rsdp, rsdt, NULL);
  487. +       acpi_write_rsdt(rsdt);
  488. +
  489. +       /* We explicitly add these tables later on: */
  490. +       printk(BIOS_DEBUG, "ACPI:     * FACS\n");
  491. +       facs = (acpi_facs_t *) current;
  492. +       current += sizeof(acpi_facs_t);
  493. +       acpi_create_facs(facs);
  494. +
  495. +       dsdt = (acpi_header_t *)current;
  496. +       memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
  497. +       current += dsdt->length;
  498. +       memcpy(dsdt, &AmlCode, dsdt->length);
  499. +       dsdt->checksum = 0;     /* Don't trust iasl to get this right. */
  500. +       dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length);
  501. +       printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
  502. +                    dsdt->length);
  503. +       printk(BIOS_DEBUG, "ACPI:     * FADT\n");
  504. +
  505. +       fadt = (acpi_fadt_t *) current;
  506. +       current += sizeof(acpi_fadt_t);
  507. +
  508. +       acpi_create_fadt(fadt, facs, dsdt);
  509. +       acpi_add_table(rsdp, fadt);
  510. +
  511. +       /* If we want to use HPET timers Linux wants it in MADT. */
  512. +       printk(BIOS_DEBUG, "ACPI:    * MADT\n");
  513. +       madt = (acpi_madt_t *) current;
  514. +       acpi_create_madt(madt);
  515. +       current += madt->header.length;
  516. +       acpi_add_table(rsdp, madt);
  517. +       printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
  518. +       mcfg = (acpi_mcfg_t *) current;
  519. +       acpi_create_mcfg(mcfg);
  520. +       current += mcfg->header.length;
  521. +       acpi_add_table(rsdp, mcfg);
  522. +
  523. +       printk(BIOS_DEBUG, "ACPI:    * SRAT\n");
  524. +       srat = (acpi_srat_t *) current;
  525. +       acpi_create_srat(srat);
  526. +       current += srat->header.length;
  527. +       acpi_add_table(rsdp, srat);
  528. +
  529. +       printk(BIOS_INFO, "ACPI: done.\n");
  530. +       return current;
  531. +}
  532. Index: src/mainboard/asus/p2b/dsdt.asl
  533. ===================================================================
  534. --- src/mainboard/asus/p2b/dsdt.asl     (revision 0)
  535. +++ src/mainboard/asus/p2b/dsdt.asl     (revision 0)
  536. @@ -0,0 +1,141 @@
  537. +/*
  538. + * This file is part of the coreboot project.
  539. + *
  540. + * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
  541. + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
  542. + *
  543. + * This program is free software; you can redistribute it and/or modify
  544. + * it under the terms of the GNU General Public License as published by
  545. + * the Free Software Foundation; version 2 of the License.
  546. + *
  547. + * This program is distributed in the hope that it will be useful,
  548. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  549. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  550. + * GNU General Public License for more details.
  551. + *
  552. + * You should have received a copy of the GNU General Public License
  553. + * along with this program; if not, write to the Free Software
  554. + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  555. + */
  556. +
  557. +/*
  558. + * ISA portions taken from QEMU acpi-dsdt.dsl.
  559. + */
  560. +
  561. +DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
  562. +{
  563. +       /* Define the main processor.*/
  564. +       Scope (\_PR)
  565. +       {
  566. +               Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}
  567. +               Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {}
  568. +       }
  569. +
  570. +       /* For now only define 2 power states:
  571. +        *  - S0 which is fully on
  572. +        *  - S5 which is soft off
  573. +        * Any others would involve declaring the wake up methods.
  574. +        */
  575. +       Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 })
  576. +       Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 })
  577. +
  578. +       /* Root of the bus hierarchy */
  579. +       Scope (\_SB)
  580. +       {
  581. +               /* Top PCI device */
  582. +               Device (PCI0)
  583. +               {
  584. +                       Name (_HID, EisaId ("PNP0A03"))
  585. +                       Name (_ADR, 0x00)
  586. +                       Name (_UID, 0x00)
  587. +                       Name (_BBN, 0x00)
  588. +
  589. +                       /* PCI Routing Table */
  590. +                       /* aaa */
  591. +                       Name (_PRT, Package () {
  592. +                               Package (0x04) { 0x0001FFFF, 0, 0, 0xB },
  593. +                               Package (0x04) { 0x0004FFFF, 3, 0, 0xB }, // { dev, int pin, static routing 0/1, irq }
  594. +
  595. +                               Package (0x04) { 0x0009FFFF, 0, 0, 0xB },
  596. +                               Package (0x04) { 0x0009FFFF, 1, 0, 0xB },
  597. +                               Package (0x04) { 0x0009FFFF, 2, 0, 0xB },
  598. +                               Package (0x04) { 0x0009FFFF, 3, 0, 0xB },
  599. +
  600. +                               Package (0x04) { 0x000AFFFF, 0, 0, 0xB },
  601. +                               Package (0x04) { 0x000AFFFF, 1, 0, 0xB },
  602. +                               Package (0x04) { 0x000AFFFF, 2, 0, 0xB },
  603. +                               Package (0x04) { 0x000AFFFF, 3, 0, 0xB },
  604. +
  605. +                               Package (0x04) { 0x000BFFFF, 0, 0, 0xB },
  606. +                               Package (0x04) { 0x000BFFFF, 1, 0, 0xB },
  607. +                               Package (0x04) { 0x000BFFFF, 2, 0, 0xB },
  608. +                               Package (0x04) { 0x000BFFFF, 3, 0, 0xB },
  609. +
  610. +                               Package (0x04) { 0x000CFFFF, 0, 0, 0xB },
  611. +                               Package (0x04) { 0x000CFFFF, 1, 0, 0xB },
  612. +                               Package (0x04) { 0x000CFFFF, 2, 0, 0xB },
  613. +                               Package (0x04) { 0x000CFFFF, 3, 0, 0xB },
  614. +                       })
  615. +
  616. +                       Device (ISA) {
  617. +                               Name (_ADR, 0x00110000)
  618. +
  619. +                               /* PS/2 keyboard (seems to be important for WinXP install) */
  620. +                               Device (KBD)
  621. +                               {
  622. +                                       Name (_HID, EisaId ("PNP0303"))
  623. +                                       Method (_STA, 0, NotSerialized)
  624. +                                       {
  625. +                                               Return (0x0f)
  626. +                                       }
  627. +                                       Method (_CRS, 0, NotSerialized)
  628. +                                       {
  629. +                                               Name (TMP, ResourceTemplate () {
  630. +                                                       IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
  631. +                                                       IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
  632. +                                                       IRQNoFlags () {1}
  633. +                                               })
  634. +                                               Return (TMP)
  635. +                                       }
  636. +                               }
  637. +
  638. +                               /* PS/2 mouse */
  639. +                               Device (MOU)
  640. +                               {
  641. +                                       Name (_HID, EisaId ("PNP0F13"))
  642. +                                       Method (_STA, 0, NotSerialized)
  643. +                                       {
  644. +                                               Return (0x0f)
  645. +                                       }
  646. +                                       Method (_CRS, 0, NotSerialized)
  647. +                                       {
  648. +                                               Name (TMP, ResourceTemplate () {
  649. +                                                    IRQNoFlags () {12}
  650. +                                               })
  651. +                                               Return (TMP)
  652. +                                       }
  653. +                               }
  654. +
  655. +                               /* PS/2 floppy controller */
  656. +                               Device (FDC0)
  657. +                               {
  658. +                                       Name (_HID, EisaId ("PNP0700"))
  659. +                                       Method (_STA, 0, NotSerialized)
  660. +                                       {
  661. +                                               Return (0x0f)
  662. +                                       }
  663. +                                       Method (_CRS, 0, NotSerialized)
  664. +                                       {
  665. +                                               Name (BUF0, ResourceTemplate () {
  666. +                                                       IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
  667. +                                                       IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
  668. +                                                       IRQNoFlags () {6}
  669. +                                                       DMA (Compatibility, NotBusMaster, Transfer8) {2}
  670. +                                               })
  671. +                                               Return (BUF0)
  672. +                                       }
  673. +                               }
  674. +                       }
  675. +               }
  676. +       }
  677. +}
  678. Index: src/northbridge/intel/i440bx/raminit.c
  679. ===================================================================
  680. --- src/northbridge/intel/i440bx/raminit.c      (revision 5402)
  681. +++ src/northbridge/intel/i440bx/raminit.c      (working copy)
  682. @@ -925,7 +925,7 @@
  683.         set_dram_row_attributes();
  684.  
  685.         /* TODO: Set SDRAMC. */
  686. -       pci_write_config16(NB, SDRAMC, 0x0010); /* SDRAMPWR=1: 4 DIMM config */
  687. +       pci_write_config16(NB, SDRAMC, 0x0000); /* SDRAMPWR=0: 3 DIMM config */
  688.  
  689.         /* TODO */
  690.         set_dram_buffer_strength();
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