vhdlfile

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-- Company:
-- Engineer:
--
-- Create Date: 15.05.2018 09:06:49
-- Design Name:
-- Module Name: Project1 - Project1_Arch
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Project1 is
    port (clkin, x1, x2, x3, x4: in bit;
          clk, y1, y2, y3, y4: out bit);
end Project1;

architecture Project1_Arch of Project1 is

component SCH
    Port (a: in bit;
          b: out bit_vector (2 downto 0));
end component;

component comp
    Port (a: in bit_vector (2 downto 0);
          b: out bit);
end component;

signal s1: bit_vector (2 downto 0);

begin
    SCH1: SCH port map (clkin, s1);
    comp1 : comp port map (s1, clk);
    y1 <= x1;
    y2 <= x2;
    y3 <= x3;
    y4 <= x4;
end Project1_Arch;

entity SCH is
    Port (a: in bit;
          b: out bit_vector (2 downto 0));
end SCH;

architecture SCH_Arch of SCH is
    begin
    process(a)
    variable sum1: integer;
    begin
        if ((a'event) and (a = '1')) then
            sum1 := sum1 + 1;
            if (sum1 = 8) then
                sum1 := 0;
            end if;
            case sum1 is
                when 0 => b <= "000";
                when 1 => b <= "001";
                when 2 => b <= "010";
                when 3 => b <= "011";
                when 4 => b <= "100";
                when 5 => b <= "101";
                when 6 => b <= "110";
                when 7 => b <= "111";
                when others =>
            end case;
        end if;
    end process;
end  SCH_Arch;

entity comp is
    Port (a: in bit_vector (2 downto 0);
          b: out bit);
end comp;

architecture comp_Arch of comp is
    begin
        b <= a(0);
end  comp_Arch;