Kaskadna veza

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;

entity MAC_KASKADNA is
    generic(input_data_width: natural := 16);
    Port ( clk_i : in STD_LOGIC;
           ce_i : in STD_LOGIC;
           u_i : in STD_LOGIC_VECTOR (input_data_width-1 downto 0);
           b_i : in STD_LOGIC_VECTOR (input_data_width-1 downto 0);
           b_j : in STD_LOGIC_VECTOR (input_data_width-1 downto 0);
           b_k : in STD_LOGIC_VECTOR (input_data_width-1 downto 0);
           o_i : out STD_LOGIC_VECTOR (2*input_data_width-1 downto 0));
end MAC_KASKADNA;

architecture Behavioral of MAC_KASKADNA is
    signal reg1, reg2 : STD_LOGIC_VECTOR (input_data_width-1 downto 0):=(others=>'0');
    signal pom : STD_LOGIC_VECTOR (input_data_width-1 downto 0):=(others=>'0');
begin
    process(clk_i)
    begin
        if (clk_i'event and clk_i = '1')then
            if (ce_i = '1') then
                reg1 <= u_i;
                reg2 <= reg1;
            end if;
        end if;
    end process;
    o_i <= std_logic_vector ((signed(reg1) * signed(b_j)) + (signed(u_i) * signed(b_i)) + (signed(reg2) * signed(b_k)));

end Behavioral;