Oct 31st, 2020
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  1. library IEEE;
  2. use IEEE.std_logic_1164.all;
  3. use IEEE.std_logic_arith.all;
  4. use IEEE.std_logic_misc.all;
  5. use IEEE.std_logic_unsigned.all;
  7. entity Counter3_tl is
  8.     port (Output: OUT STD_LOGIC);
  9. end Counter3_tl;
  11. architecture Counter3_tl_arch of Counter3_tl is
  12.     component Counter3
  13.         port (Input: IN STD_LOGIC);
  14.     end component;
  15.     signal INP : STD_LOGIC;
  16.     signal OUTP : STD_LOGIC;
  17.         begin
  18.         Counter3_1 : Counter3 port map (    Input => INP,
  19.                                             Output => OUTP);
  20. end Counter3_tl_arch;
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