library ieee;
use IEEE.Std_Logic_1164.all;
use IEEE.numeric_std.all;

entity tb_Config is
end tb_Config;

architecture Test of tb_Config is

component secondDevice
    port(D : in std_logic_vector ( 3 downto 0);
       I, E, S, C, R: in std_logic;
       Q: inout std_logic_vector ( 3 downto 0)
    );
end component;


signal  in_D : std_logic_vector ( 3 downto 0) := "0000";
signal  in_I, in_E, in_S, in_C,in_R: std_logic:= '0';
signal  out_Q_STR, out_Q_RTL, out_Q_BEH : std_logic_vector ( 3 downto 0);

begin
p1 : secondDevice port map(in_D, in_I, in_E, in_S, in_C, in_R, out_Q_STR);
p2 : secondDevice port map(in_D, in_I, in_E, in_S, in_C, in_R, out_Q_RTL);
p3 : secondDevice port map(in_D, in_I, in_E, in_S, in_C, in_R, out_Q_BEH);
p4 : process
     begin
       in_D <= std_logic_vector(unsigned(in_D) + 1);
       wait for 20 ns;
     end process;
p5 : process
     begin
       in_I <= '0';
       wait for 800 ns;
       in_I <= '1';
       wait for 800 ns;
     end process;
p6 : process
     begin
       in_E <= '0';
       wait for 3200 ns;
       in_E <= '1';
       wait for 3200 ns;
     end process;
p7 : in_S <= '0'after 0 ns, '1'after 1900ns, '0'after 1905 ns,'1'after 2200ns, '0'after 2205 ns;
p8 : process
     begin
       in_C <= not in_C;
       wait for 7 ns;
     end process;
p9 :in_R <= '0'after 0 ns, '1'after 1900ns, '0'after 1905 ns, '1'after 2700ns, '0'after 2705 ns;
end Test;