uBoot board init

struct display_info_t const displays[] = {{
    .bus    = -1,
    .addr   = 0,
    .pixfmt = IPU_PIX_FMT_LVDS666,
    .detect = NULL,
    .enable = enable_lvds,
    .mode   = {
        .name           = "LDB-XGA",
        .refresh        = 60,
        .xres           = 1024,
        .yres           = 600,
        .pixclock       = 19531, /* ~51.2MHz */
        .left_margin    = 160,
        .right_margin   = 140,
        .hsync_len      = 20,
        .upper_margin   = 20,
        .lower_margin   = 12,
        .vsync_len      = 3,
        .sync           = FB_SYNC_EXT,
        .vmode          = FB_VMODE_NONINTERLACED
} }, {
    .bus    = -1,
    .addr   = 0,
    .pixfmt = IPU_PIX_FMT_RGB24,
    .detect = NULL,
    .enable = do_enable_hdmi,
    .mode   = {
        .name           = "HDMI",
        .refresh        = 60,
        .xres           = 1280,
        .yres           = 720,
        .pixclock       = 15385,
        .left_margin    = 220,
        .right_margin   = 40,
        .upper_margin   = 21,
        .lower_margin   = 7,
        .hsync_len      = 60,
        .vsync_len      = 10,
        .sync           = FB_SYNC_EXT,
        .vmode          = FB_VMODE_NONINTERLACED
} } };
size_t display_count = ARRAY_SIZE(displays);

static void setup_display(void)
{
    struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
    struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
    int reg;

    enable_ipu_clock();
    imx_setup_hdmi();

    /* Turn on LDB0,IPU,IPU DI0 clocks */
    reg = __raw_readl(&mxc_ccm->CCGR3);
    reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
    writel(reg, &mxc_ccm->CCGR3);

    /* set LDB0, LDB1 clk select to 011/011 */
    reg = readl(&mxc_ccm->cs2cdr);
    reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
         |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
    reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
          |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
    writel(reg, &mxc_ccm->cs2cdr);

    reg = readl(&mxc_ccm->cscmr2);
    reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
    writel(reg, &mxc_ccm->cscmr2);

    reg = readl(&mxc_ccm->chsccdr);
    reg |= (CHSCCDR_CLK_SEL_LDB_DI0
        <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
    writel(reg, &mxc_ccm->chsccdr);

    reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
         |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
         |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
         |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
         |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
         |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
         |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
         |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
         |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
    writel(reg, &iomux->gpr[2]);

    reg = readl(&iomux->gpr[3]);
    reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
            |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
        | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
           <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
    writel(reg, &iomux->gpr[3]);

    /* backlights off until needed */
    imx_iomux_v3_setup_multiple_pads(display_power_pads,
                     ARRAY_SIZE(display_power_pads));
    gpio_direction_input(LVDS_BACKLIGHT_PWM);
    gpio_direction_input(LVDS_POWER_SHDN);
    gpio_direction_input(LVDS_POWER_RDY);

}
#endif /* CONFIG_VIDEO_IPUV3 */