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- module uc(
- clk,
- rst,
- ri,
- ind,
- regs_addr,
- regs_oe,
- regs_we,
- alu_oe,
- alu_carry,
- alu_opcode,
- ram_oe,
- ram_we,
- io_oe,
- io_we,
- cp_oe,
- cp_we,
- ind_sel,
- ind_oe,
- ind_we,
- am_oe,
- am_we,
- aie_oe,
- aie_we,
- t1_oe,
- t1_we,
- t2_oe,
- t2_we,
- ri_oe,
- ri_we,
- disp_state
- );
- parameter word_width = 16;
- parameter state_width = 16;
- input clk;
- input rst;
- input [word_width-1 : 0] ri;
- input [word_width-1 : 0] ind;
- output reg alu_oe;
- output reg alu_carry;
- output reg[3 : 0] alu_opcode;
- output reg ram_oe;
- output reg ram_we;
- output reg io_oe;
- output reg io_we;
- output reg[2 : 0] regs_addr;
- output reg regs_oe;
- output reg regs_we;
- output reg cp_oe;
- output reg cp_we;
- output reg ind_sel; // controls IND register input (0 = bus, 1 = alu flags)
- output reg ind_oe;
- output reg ind_we;
- output reg am_oe;
- output reg am_we;
- output reg aie_oe;
- output reg aie_we;
- output reg t1_oe;
- output reg t1_we;
- output reg t2_oe;
- output reg t2_we;
- output reg ri_oe; // controls RI register output which generates the offset for Jcond instructions
- output reg ri_we;
- output[state_width-1 : 0] disp_state;
- `define reset 'h00 // reset state
- `define fetch 'h10 // load instruction to instruction register
- reg [state_width-1 : 0] state = `reset, state_next;
- // FSM - sequential part
- always @(posedge clk) begin
- state <= `reset;
- if(!rst)
- state <= state_next;
- end
- // FSM - combinational part
- always @(*) begin
- state_next = `reset;
- alu_oe = 0;
- alu_carry = 0;
- alu_opcode = 0;
- ram_oe = 0;
- ram_we = 0;
- io_oe = 0;
- io_we = 0;
- regs_addr = 0;
- regs_oe = 0;
- regs_we = 0;
- cp_oe = 0;
- cp_we = 0;
- ind_sel = 0;
- ind_oe = 0;
- ind_we = 0;
- am_oe = 0;
- am_we = 0;
- aie_oe = 0;
- aie_we = 0;
- t1_oe = 0;
- t1_we = 0;
- t2_oe = 0;
- t2_we = 0;
- ri_oe = 0;
- ri_we = 0;
- case(state)
- `reset: begin
- state_next = `fetch;
- end
- `fetch: begin
- cp_oe = 1;
- am_we = 1;
- state_next = `fetch + 1;
- end
- `fetch + 'd1: begin
- am_oe = 1;
- state_next = `fetch + 2;
- end
- `fetch + 'd2: begin
- ram_oe = 1;
- ri_we = 1;
- state_next = `reset;
- end
- default: ;
- endcase
- end
- assign disp_state = state;
- endmodule
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