/* Includes *******************************************************************/
#include <io.h>
#include <malloc.h>
#include <system.h>
#include <unistd.h>

#include <sys/alt_timestamp.h>
#include <altera_avalon_timer_regs.h>
#include "altera_msgdma.h"
#include "altera_eth_tse.h"
#include "altera_eth_tse_regs.h"
#include "altera_avalon_tse.h"
#include "altera_avalon_tse_system_info.h"

unsigned char __attribute__((section(".sdram"))) tx_frame[1024] = {
0x01,0x00,
0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
0x01,0x60,0x6E,0x11,0x02,0x0F,
0x00,0x2E,
'T', 'E', 'S', 'T', '\0'
};


void tse_init(void)
{
    np_tse_mac *pmac = (np_tse_mac*)TSE_0_TSE_BASE;

    alt_tse_system_mac sys_mac = {TSE_SYSTEM_MAC(TSE_0_TSE)};
    alt_tse_system_msgdma sys_msgdma = {TSE_SYSTEM_MSGDMA(TSE_0_DMA_TX, TSE_0_DMA_RX)};
    alt_tse_system_desc_mem sys_mem = {TSE_SYSTEM_NO_DESC_MEM()};
    alt_tse_system_shared_fifo sys_sfifo = {TSE_SYSTEM_NO_SHARED_FIFO()};
    alt_tse_system_phy sys_phy = {TSE_SYSTEM_PHY(TSE_PHY_AUTO_ADDRESS, &marvell_phy_cfg)};

    if(alt_tse_system_add_sys(&sys_mac, &sys_msgdma, &sys_mem, &sys_sfifo, &sys_phy) != SUCCESS) {
        printf("could not add TSE MAC system\n");
        return;
    }

    alt_u32 ctrl = 0;
    alt_msgdma_standard_descriptor tx_desc;
    alt_msgdma_dev *dev = alt_msgdma_open(TSE_0_DMA_TX_CSR_NAME);
    if(dev == NULL) {
        printf("could not open msgdma tx device\n");
        return;
    }

    //Set MAC address
    IOWR_ALTERA_TSEMAC_MAC_0(TSE_0_TSE_BASE, 0x116E6001);
    IOWR_ALTERA_TSEMAC_MAC_1(TSE_0_TSE_BASE, 0x00000F02);

    ctrl |= ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MASK;
    ctrl |= ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_SOP_MASK;

    //Software-reset PHY chip
    tse_mac_SwReset(pmac);
    //IOWR_32DIRECT(TSE_0_TSE_BASE, 0x80*4, IORD_32DIRECT(TSE_0_TSE_BASE, 0x80*4) | 0x8000);
    //while(IORD_32DIRECT(TSE_0_TSE_BASE, 0x80*4) & 0x8000); //wait

    //Enable write transfers, gigabit Ethernet operation
    IOWR_ALTERA_TSEMAC_CMD_CONFIG(TSE_0_TSE_BASE, IORD_ALTERA_TSEMAC_CMD_CONFIG(TSE_0_TSE_BASE) | 0x00000009);

    alt_u32 *read_addr = (alt_u32 *)&tx_frame[0];
    if(alt_msgdma_construct_standard_mm_to_st_descriptor(dev, &tx_desc, read_addr, 1024, ctrl) != 0) {
        printf("could not construct tx descriptor\n");
        return;
    }
    ctrl |= ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK;

    if(alt_msgdma_standard_descriptor_async_transfer(dev, &tx_desc) != 0) {
        printf("could not start async transfer. status reg: 0x%x\n", IORD_ALTERA_MSGDMA_CSR_STATUS(TSE_0_DMA_TX_CSR_BASE));
        return;
    }
}

/* main ***********************************************************************/
int main(void)
{
    tse_init();
    while(1);
}