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Feb 24th, 2019
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  1. /* Includes *******************************************************************/
  2. #include <io.h>
  3. #include <malloc.h>
  4. #include <system.h>
  5. #include <unistd.h>
  6.  
  7. #include <sys/alt_timestamp.h>
  8. #include <altera_avalon_timer_regs.h>
  9. #include "altera_msgdma.h"
  10. #include "altera_eth_tse.h"
  11. #include "altera_eth_tse_regs.h"
  12. #include "altera_avalon_tse.h"
  13. #include "altera_avalon_tse_system_info.h"
  14.  
  15. unsigned char __attribute__((section(".sdram"))) tx_frame[1024] = {
  16. 0x01,0x00,
  17. 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
  18. 0x01,0x60,0x6E,0x11,0x02,0x0F,
  19. 0x00,0x2E,
  20. 'T', 'E', 'S', 'T', '\0'
  21. };
  22.  
  23.  
  24. void tse_init(void)
  25. {
  26.     np_tse_mac *pmac = (np_tse_mac*)TSE_0_TSE_BASE;
  27.  
  28.     alt_tse_system_mac sys_mac = {TSE_SYSTEM_MAC(TSE_0_TSE)};
  29.     alt_tse_system_msgdma sys_msgdma = {TSE_SYSTEM_MSGDMA(TSE_0_DMA_TX, TSE_0_DMA_RX)};
  30.     alt_tse_system_desc_mem sys_mem = {TSE_SYSTEM_NO_DESC_MEM()};
  31.     alt_tse_system_shared_fifo sys_sfifo = {TSE_SYSTEM_NO_SHARED_FIFO()};
  32.     alt_tse_system_phy sys_phy = {TSE_SYSTEM_PHY(TSE_PHY_AUTO_ADDRESS, &marvell_phy_cfg)};
  33.  
  34.     if(alt_tse_system_add_sys(&sys_mac, &sys_msgdma, &sys_mem, &sys_sfifo, &sys_phy) != SUCCESS) {
  35.         printf("could not add TSE MAC system\n");
  36.         return;
  37.     }
  38.  
  39.     alt_u32 ctrl = 0;
  40.     alt_msgdma_standard_descriptor tx_desc;
  41.     alt_msgdma_dev *dev = alt_msgdma_open(TSE_0_DMA_TX_CSR_NAME);
  42.     if(dev == NULL) {
  43.         printf("could not open msgdma tx device\n");
  44.         return;
  45.     }
  46.  
  47.     //Set MAC address
  48.     IOWR_ALTERA_TSEMAC_MAC_0(TSE_0_TSE_BASE, 0x116E6001);
  49.     IOWR_ALTERA_TSEMAC_MAC_1(TSE_0_TSE_BASE, 0x00000F02);
  50.  
  51.     ctrl |= ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MASK;
  52.     ctrl |= ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_SOP_MASK;
  53.  
  54.     //Software-reset PHY chip
  55.     tse_mac_SwReset(pmac);
  56.     //IOWR_32DIRECT(TSE_0_TSE_BASE, 0x80*4, IORD_32DIRECT(TSE_0_TSE_BASE, 0x80*4) | 0x8000);
  57.     //while(IORD_32DIRECT(TSE_0_TSE_BASE, 0x80*4) & 0x8000); //wait
  58.  
  59.     //Enable write transfers, gigabit Ethernet operation
  60.     IOWR_ALTERA_TSEMAC_CMD_CONFIG(TSE_0_TSE_BASE, IORD_ALTERA_TSEMAC_CMD_CONFIG(TSE_0_TSE_BASE) | 0x00000009);
  61.  
  62.     alt_u32 *read_addr = (alt_u32 *)&tx_frame[0];
  63.     if(alt_msgdma_construct_standard_mm_to_st_descriptor(dev, &tx_desc, read_addr, 1024, ctrl) != 0) {
  64.         printf("could not construct tx descriptor\n");
  65.         return;
  66.     }
  67.     ctrl |= ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK;
  68.  
  69.     if(alt_msgdma_standard_descriptor_async_transfer(dev, &tx_desc) != 0) {
  70.         printf("could not start async transfer. status reg: 0x%x\n", IORD_ALTERA_MSGDMA_CSR_STATUS(TSE_0_DMA_TX_CSR_BASE));
  71.         return;
  72.     }
  73. }
  74.  
  75. /* main ***********************************************************************/
  76. int main(void)
  77. {
  78.     tse_init();
  79.     while(1);
  80. }
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